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| 型號： | CS80C286-12 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 56/60頁 |
| 文件大小： | 0K |
| 描述： | IC CPU 16BIT 5V 12.5MHZ 68-PLCC |
| 標準包裝： | 126 |
| 處理器類型： | 80C286 16-位 |
| 速度： | 12.5MHz |
| 電壓： | 5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 供應商設備封裝： | 68-PLCC（24.23x24.23） |
| 包裝： | 管件 |
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6
Functional Description
Introduction
The Intersil 80C286 microprocessor is a static CMOS ver-
sion of the NMOS 80286 microprocessor. The 80C286 is an
advanced, high-performance microprocessor with specially
optimized capabilities for multiple user and multi-tasking sys-
tems. Depending on the application, the 80C286's perfor-
mance is up to nineteen times faster than the standard
5MHz 8086's, while providing complete upward software
compatibility with Intersil 80C86 and 80C88 CPU family.
The 80C286 operates in two modes: 80C286 real address
mode and protected virtual address mode. Both modes exe-
cute a superset of the 80C86 and 80C88 instruction set.
In 80C286 real address mode programs use real addresses
with up to one megabyte of address space. Programs use vir-
tual addresses in protected virtual address mode, also called
protected mode. In protected mode, the 80C286 CPU automat-
ically maps 1 gigabyte of virtual addresses per task into a 16
megabyte real address space. This mode also provides mem-
ory protection to isolate the operating system and ensure pri-
vacy of each tasks' programs and data. Both modes provide
the same base instruction set, registers and addressing modes.
The Functional Description describes the following: Static oper-
ation, the base 80C286 architecture common to both modes,
80C286 real address mode, and finally, protected mode.
Static Operation
The 80C286 is comprised of completely static circuitry.
Internal registers, counters, and latches are static and
require no refresh as with dynamic circuit design. This elim-
inates the minimum operating frequency restriction typically
placed on microprocessors. The CMOS 80C286 can oper-
ate from DC to the specified upper frequency limit. The
clock to the processor may be stopped at any point (either
phase one or phase two of the processor clock cycle) and
held there indefinitely. There is, however, a significant
decrease in power requirement if the clock is stopped in
phase two of the processor clock cycle. Details on the clock
relationships will be discussed in the Bus Operation sec-
tion. The ability to stop the clock to the processor is espe-
cially useful for system debug or power critical applications.
RESET
29
l
SYSTEM RESET: clears the internal logic of the 80C286 and is active HIGH. The 80C286 may be
reinitialize at any time with a LOW to HIGH transition on RESET which remains active for more than
16 system clock cycles. During RESET active, the output pins of the 80C286 enter the state shown
below.
Operation of the 80C286 begins after a HlGH to LOW transition on RESET. The HIGH to LOW
transition of RESET must be synchronous to the system clock. Approximately 50 system clock
cycles are required by the 80C286 for internal initializations before the first bus cycle to fetch code
from the power-on execution address is performed. A LOW to HIGH transition of RESET
synchronous to the system clock will end a processor cycle at the second HIGH to LOW transition
of the system clock. The LOW to HIGH transition of RESET may be asynchronous to the system
clock; however, in this case it cannot be predetermined which phase of the processor clock will occur
during the next system clock period. Synchronous LOW to HIGH transitions of RESET are required
only for systems where the processor clock must be phase synchronous to another clock.
VSS
9, 35, 60
l
SYSTEM GROUND: are the ground pins (all must be connected to system ground).
VCC
30, 62
l
SYSTEM POWER: +5V power supply pins. A 0.1
μF capacitor between pins 60 and 62 is recommended.
NOTES:
1. READY is an open-collector signal and should be pulled inactive with an appropriate resistor (620
Ω at 10MHz and 12.5MHz, 470Ω at
16MHz, 390
Ω at 20MHz, 270Ω at 25MHz).
2. HLDA is only Low if HOLD is inactive (Low).
3. All unused inputs should be pulled to their inactive state with pull up/down resistors.
Pin Descriptions The following pin function descriptions are for the 80C286 microprocessor. (Continued)
SYMBOL
PIN
NUMBER
TYPE
DESCRIPTION
80C286 PIN STATE DURING RESET
PIN VALUE
PIN NAMES
1 (HIGH)
S0, S1, PEACK, A23 - A0, BHE, LOCK
0 (LOW)
M/IO, COD/lNTA, HLDA (Note 2)
HIGH IMPEDANCE
D15 - D0
80C286
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CS80C286-1296 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CS80C286-12X136 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CS80C286-16 | 功能描述:微處理器 - MPU CPU 16BIT 5V CMOS 16 MHZ 68PLCC COM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| CS80C286-1696 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CS80C286-2 | 制造商:Harris Corporation 功能描述: |
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