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| 型號： | CS80C286-12 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 17/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPU 16BIT 5V 12.5MHZ 68-PLCC |
| 標(biāo)準(zhǔn)包裝： | 126 |
| 處理器類型： | 80C286 16-位 |
| 速度： | 12.5MHz |
| 電壓： | 5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 68-PLCC（24.23x24.23） |
| 包裝： | 管件 |
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The lRET and POPF instructions do not perform some of
their defined functions if CPL is not of sufficient privilege
(numerically small enough). Precisely these are:
The IF bit is not changed if CPL is greater than IOPL.
The lOPL field of the flag word is not changed if CPL is
greater than 0.
No exceptions or other indication are given when these con-
ditions occur.
Exceptions
The 80C286 detects several types of exceptions and inter-
rupts in protected mode (see Table 17). Most are restartable
after the exceptional condition is removed. Interrupt handlers
for most exceptions can read an error code, pushed on the
stack after the return address, that identifies the selector
involved (0 if none). The return address normally points to
the failing instruction including all leading prefixes. For a pro-
cessor extension segment overrun exception, the return
address will not point at the ESC instruction that caused the
exception; however, the processor extension registers may
contain the address of the failing instruction.
These exceptions indicate a violation to privilege rules or
usage rules has occurred. Restart is generally not attempted
under those conditions.
All these checks are performed for all instructions and can
be split into three categories: segment load checks (Table
14), operand reference checks (Table 15), and privileged
instruction checks (Table 16). Any violation of the rules
shown will result in an exception. A not-present exception
causes exception 11 or 12 and is restartable.
SPECIAL OPERATIONS
Task Switch Operation
The 80C286 provides a built-in task switch operation which
saves the entire 80C286 execution state (registers, address
space, and a link to the previous task), loads a new execution
state, and commences execution in the new task. Like gates,
the task switch operation is invoked by executing an inter-seg-
ment JMP or CALL instruction which refers to a Task State
Segment (TSS) or task gate descriptor in the GDT or LDT. An
INT instruction, exception, or external interrupt may also
invoke the task switch operation by selecting a task gate
descriptor in the associated IDT descriptor entry.
The TSS descriptor points at a segment (see Figure 18) con-
taining the entire 80C286 execution state while a task gate
descriptor contains a TSS selector. The limit field of the
descriptor must be greater than 002B(H).
Each task must have a TSS associated with it. The current
TSS is identified by a special register in the 80C286 called
the Task Register (TR). This register contains a selector
referring to the task state segment descriptor that defines
the current TSS. A hidden base and limit register associated
with TR are loaded whenever TR is loaded with a new selec-
tor. The IRET instruction is used to return control to the task
that called the current task or was interrupted. Bit 14 in the
flag register is called the Nested Task (NT) bit. It controls the
TABLE 15. OPERAND REFERENCE CHECKS
ERROR DESCRIPTION
EXCEPTION
NUMBER
Write into code segment
13
Read from execute-only code segment
13
Write to read-only data segment
13
Segment limit exceeded (See Note)
12 or 13
NOTE: Carry out in offset calculations is ignored.
TABLE 16. PRIVILEGED INSTRUCTION CHECKS
ERROR DESCRIPTION
EXCEPTION
NUMBER
CPL
≠ 0 when executing the following instructions:
LIDT, LLDT, LGDT, LTR, LMSW, CTS, HLT
13
CPT > IOPL when executing the following
instructions:
INS, IN, OUTS, OUT, STI, CLI, LOCK
13
TABLE 17. PROTECTED MODE EXCEPTIONS
INTERRUPT
VECTOR
FUNCTION
RETURN ADDRESS
AT FALLING
INSTRUCTION?
ALWAYS
RESTARTABLE?
ERROR CODE
ON STACK?
8
Double exception detected
Yes
No (Note 7)
Yes
9
Processor extension segment overrun
No
No (Note 7)
No
10
Invalid task state segment
Yes
11
Segment not present
Yes
12
Stack segment overrun or stack segment not present
Yes
Yes (Note 6)
Yes
13
General protection
Yes
No (Note 7)
Yes
NOTES:
6. When a PUSHA or POPA instruction attempts to wrap around the stack segment, the machine state after the exception will not be restartable
because stack segment wrap around is not permitted. This condition is identified by the value of the saved SP being either 0000(H), 0001(H),
FFFE(H), or FFFF(H).
7. These exceptions indicate a violation to privilege rules or usage rules has occurred. Restart is generally not attempted under those conditions.
80C286
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相關(guān)代理商/技術(shù)參數(shù) |
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| CS80C286-1296 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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| CS80C286-16 | 功能描述:微處理器 - MPU CPU 16BIT 5V CMOS 16 MHZ 68PLCC COM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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| CS80C286-2 | 制造商:Harris Corporation 功能描述: |
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