參數(shù)資料
型號(hào): CP2201EK
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 45/108頁(yè)
文件大?。?/td> 0K
描述: KIT EVAL FOR CP2201 ETH CTRLR
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,以太網(wǎng)傳感器
嵌入式: 是,MCU,8 位
已用 IC / 零件: CP2200,CP2201
主要屬性: 溫度和光傳感器
次要屬性: 圖形用戶界面
已供物品: 板,電源,線纜,CD
產(chǎn)品目錄頁(yè)面: 627 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: 336-1313-ND - IC ETH CTRLR SNGL-CHIP 28QFN
336-1312-ND - IC ETH CTRLR SNGL-CHIP 48TQFP
其它名稱: 336-1316
CP2200/1
Rev. 1.0
41
9.6. Determining the Source of the Last Reset
The RSTSTA register can be used to determine the cause of the last reset. Note: If the PORSI bit is set to logic 1,
all other bits in RSTSTA are undefined. It is impossible to differentiate between a power-on, power-fail, and
oscillator-fail reset by reading the RSTSTA register.
Register 13. RSTSTA: Reset Source Status Register
Bits 7–3: UNUSED. Read = 00000b, Write = don’t care.
Bit 2:
SWRSI: Software Reset Indicator
0: Source of last reset was not a write to RESET (SWRESET.2).
1: Source of last reset was a write to RESET (SWRESET.2).
Bit 1:
PORSI: Power-On / Power-Fail / Oscillator-Fail Reset Indicator
0: Source of last reset was not a power-on, power-fail, or oscillator-fail event.
1: Source of last reset was a power-on, power-fail, or oscillator-fail event.
Bit 0:
PINRSI: External Pin Reset Indicator
0: Source of last reset was not the /RST pin.
1: Source of last reset was the /RST pin.
R/W
R
Reset Value
SWRSI
PORSI
PINRSI
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x73
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