參數(shù)資料
型號: CP2201EK
廠商: Silicon Laboratories Inc
文件頁數(shù): 36/108頁
文件大?。?/td> 0K
描述: KIT EVAL FOR CP2201 ETH CTRLR
標準包裝: 1
主要目的: 接口,以太網傳感器
嵌入式: 是,MCU,8 位
已用 IC / 零件: CP2200,CP2201
主要屬性: 溫度和光傳感器
次要屬性: 圖形用戶界面
已供物品: 板,電源,線纜,CD
產品目錄頁面: 627 (CN2011-ZH PDF)
相關產品: 336-1313-ND - IC ETH CTRLR SNGL-CHIP 28QFN
336-1312-ND - IC ETH CTRLR SNGL-CHIP 48TQFP
其它名稱: 336-1316
CP2200/1
Rev. 1.0
33
Register 7. INT0EN: Interrupt Enable Register 0
Bit 7:
EEOPINT: Enable End of Packet Interrupt
0: Disable End of Packet Interrupt.
1: Enable End of Packet Interrupt.
Bit 6:
ERXEINT: Enable Receive FIFO Empty Interrupt
0: Disable Receive FIFO Empty Interrupt.
1: Enable Receive FIFO Empty Interrupt.
Bit 5:
ESELFINT: Enable Self Initialization Complete Interrupt
0: Disable Self Initialization Complete Interrupt.
1: Enable Self Initialization Complete Interrupt.
Bit 4:
EOSCINT: Enable Oscillator Initialization Complete Interrupt
0: Disable Oscillator Initialization Complete Interrupt.
1: Enable Oscillator Initialization Complete Interrupt.
Bit 3:
EFLWEINT: Enable Flash Write/Erase Operation Complete Interrupt
0: Disable Flash Write/Erase Operation Complete Interrupt.
1: Enable Flash Write/Erase Operation Complete Interrupt.
Bit 2:
ETXINT: Enable Packet Transmitted Interrupt
0: Disable Packet Transmitted Interrupt.
1: Enable Packet Transmitted Interrupt.
Bit 1:
ERXFINT: Enable Receive FIFO Full Interrupt
0: Disable Receive FIFO Full Interrupt.
1: Enable Receive FIFO Full Interrupt.
Bit 0:
ERXINT: Enable Packet Received Interrupt
0: Disable Packet Received Interrupt.
1: Enable Packet Received Interrupt.
R/W
Reset Value
EEOPINT ERXEINT ESELFINT EOSCINT EFLWEINT
ETXINT
ERXFINT
ERXINT
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x64
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