參數(shù)資料
型號: CP2201EK
廠商: Silicon Laboratories Inc
文件頁數(shù): 44/108頁
文件大?。?/td> 0K
描述: KIT EVAL FOR CP2201 ETH CTRLR
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,以太網(wǎng)傳感器
嵌入式: 是,MCU,8 位
已用 IC / 零件: CP2200,CP2201
主要屬性: 溫度和光傳感器
次要屬性: 圖形用戶界面
已供物品: 板,電源,線纜,CD
產(chǎn)品目錄頁面: 627 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: 336-1313-ND - IC ETH CTRLR SNGL-CHIP 28QFN
336-1312-ND - IC ETH CTRLR SNGL-CHIP 48TQFP
其它名稱: 336-1316
CP2200/1
40
Rev. 1.0
9.5. Software Reset
The software reset provides the host CPU the ability to reset the CP2200/1 through the parallel host interface.
Writing a ‘1’ to RESET (SWRST.2) will force the device to enter the reset state with the exception that the external
oscillator will not be stopped. As soon as the device enters the reset state, it will immediately exit the reset state
and start device calibration; the Oscillator Initialization Complete interrupt is not be generated. After Self
Initialization is complete, the device is fully functional.
Note: The software reset is enabled after every reset; however, it may be de-selected as a reset source (see the register
description for RSTEN on page 42).
Register 12. SWRST: Software Reset Register
Bits 7–3: UNUSED. Read = 00000b, Write = don’t care.
Bit 2:
RESET: Software Reset Initiate
Writing a ‘1’ to this bit will generate a software reset.
Bits 1–0: UNUSED. Read = 00b, Write = don’t care.
R\W
R/W
W
R/W
Reset Value
RESET
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x75
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