參數(shù)資料
型號： CP2201-GM
廠商： Silicon Laboratories Inc
文件頁數(shù)： 93/108頁
文件大?。?/td> 0K
描述： IC ETH CTRLR SNGL-CHIP 28QFN
標(biāo)準(zhǔn)包裝： 73
控制器類型： 以太網(wǎng)控制器，MAC/10Base-T
接口： 并行/串行
電源電壓： 3.1 V ~ 3.6 V
電流 - 電源： 75mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 28-QFN（5x5）
包裝： 管件
產(chǎn)品目錄頁面： 627 (CN2011-ZH PDF)
配用： 336-1326-ND - KIT REF DESIGN PWR OVER ETHERNET
336-1316-ND - KIT EVAL FOR CP2201 ETH CTRLR
其它名稱： 336-1313
CP2200/1
Rev. 1.0
85
Indirect Register 5. CWMAXR: Collision Window and Maximum Retransmit Register
Indirect Register 6. MAXLEN: Maximum Frame Length Register
Note: This register does not require initialization and will be left at its reset value by most systems.
Bits 15–14:Reserved. Read = 00b; Must write 00b.
Bits 13–8:CW: Collision Window
Sets the collision window in which collisions occur in a properly configured network.
The collision window is specified in the number of bytes from the start of transmission. The pream-
ble and frame delimiter are included in the byte count. Its default of 0x37 corresponds to the count
of frame bytes at the end of the window.
Bits 7–4: Reserved. Read = 0000b; Must write 0000b.
Bits 3–0: MAXR: Maximum Retransmit Attempts
Sets the maximum number of retransmit attempts following a collision before aborting the packet
due to excessive collisions. IEEE 802.3 specifies a maximum value of 0x0F (15d).
R/WR/WR/WR/WR/WR/WR/W
R/W
Reserved
CW
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
R/W
Default Value
Reserved
MAXR
0x370F
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MACADDR:
0x04
Note: This register does not require initialization and will be left at its reset value will be set to 1518 (0x05EE)
by most systems.
Bits 15–0:MAXF: Maximum Frame Length
Specifies the maximum length of a receive frame. The default value is 0x600 (1536 octets). This
register should be programmed if a shorter maximum length restriction is desired. Examples of
shorter frame lengths are untagged (1518 octets) and tagged (1522 octets). If a proprietary header
is allowed, this field should be adjusted accordingly.
R/WR/WR/WR/WR/WR/WR/W
R/W
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
R/W
Default Value
0x0600
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MACADDR:
0x05
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