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參數(shù)資料
| 型號： | CP2201-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 40/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ETH CTRLR SNGL-CHIP 28QFN |
| 標準包裝： | 73 |
| 控制器類型： | 以太網(wǎng)控制器，MAC/10Base-T |
| 接口： | 并行/串行 |
| 電源電壓： | 3.1 V ~ 3.6 V |
| 電流 - 電源： | 75mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 28-QFN（5x5） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 627 (CN2011-ZH PDF) |
| 配用： | 336-1326-ND - KIT REF DESIGN PWR OVER ETHERNET 336-1316-ND - KIT EVAL FOR CP2201 ETH CTRLR |
| 其它名稱： | 336-1313 |
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CP2200/1
Rev. 1.0
37
9. Reset Sources
Reset circuitry allows the CP2200/1 to be easily placed in a predefined default condition. Upon entry to this reset
state, the following events occur:
All direct and indirect registers are initialized to their defined reset values.
Digital pins (except /RST) are forced into a high impedance state with a weak pull-up to VDD.
Analog pins (TX+/TX–, RX+/RX–) are forced into a high impedance state without a weak pull-up.
The external oscillator is stopped and /RST driven low (except on a software reset).
All interrupts are enabled.
The contents of the transmit and receive buffers are unaffected by a reset as long as the device has maintained
sufficient supply voltage. However, since the buffer pointers are reset to their default values, the data is effectively
lost unless the host processor has kept track of the starting address and length of each packet in the buffer.
The CP2200/1 has five reset sources that place the device in the reset state. The method of entry to the reset state
determines the amount of time spent in reset and the behavior of the /RST pin. Each of the following reset sources
is described in the following sections:
Power-On
Power-Fail
Oscillator-Fail
External /RST Pin
Software Command
Upon exit from the reset state, the device automatically starts the external oscillator and waits for it to settle (this
step is skipped on software reset). Once the crystal oscillator settles, the Oscillator Initialization Complete interrupt
occurs (interrupt pin asserted), and the host processor may now access the internal registers to poll for the Self
Initialization Complete Interrupt. If the host does not have access to the interrupt signal, it should wait
approximately 1 ms after the rising edge of reset pin prior to polling the internal registers. Note that the reset pin
could remain low up to 100 ms depending on the power supply ramp time.
The device is fully functional after the Self Initialization has completed. See “6.2. Reset Initialization” on page 18 for
the recommended initialization procedure following a device reset.
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