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參數(shù)資料
| 型號： | CP2201-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 80/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ETH CTRLR SNGL-CHIP 28QFN |
| 標準包裝： | 73 |
| 控制器類型： | 以太網(wǎng)控制器，MAC/10Base-T |
| 接口： | 并行/串行 |
| 電源電壓： | 3.1 V ~ 3.6 V |
| 電流 - 電源： | 75mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 28-QFN（5x5） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 627 (CN2011-ZH PDF) |
| 配用： | 336-1326-ND - KIT REF DESIGN PWR OVER ETHERNET 336-1316-ND - KIT EVAL FOR CP2201 ETH CTRLR |
| 其它名稱： | 336-1313 |
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CP2200/1
Rev. 1.0
73
13. Flash Memory
The CP2200/1 has 8 kB of on-chip non-volatile Flash memory fully accessible by the host processor. The last six
bytes of this memory space (addresses 0x1FFA to 0x1FFF) are factory preprogrammed and contain a unique 48-
bit MAC Address (Individual Address) registered with the IEEE Registration Authority. The most significant byte of
the MAC address is at 0x1FFA, and the least significant byte is at 0x1FFF. The last page of Flash containing the
MAC address is erasable, and the user should exercise caution to prevent erasing the MAC Address.
13.1. Programming the Flash Memory
The Flash memory can be programmed one byte at a time through the parallel host interface. Once cleared to a
logic 0, a Flash bit must be erased to set it back to logic 1. A Flash bit may always be changed from logic 1 to
logic 0, as long as Flash bytes are only written once between erase cycles. Flash erase operations erase an entire
512 byte sector at a time. Flash write and erase operations are automatically timed by hardware and do not affect
the parallel host interface. After initiating a Flash write or erase operation, the host CPU can continue to access the
CP2200/1 through the parallel host interface while the Flash operation is taking place. The host is notified with an
interrupt request when the Flash write or erase operation is complete. Refer to Table 18 for complete Flash
memory electrical characteristics including typical write and erase cycle times.
The Flash memory can be written and erased using the FLASHADDRH:FLASHADDRL, FLASHDATA, and
FLASHERASE registers. Once a Flash operation is initiated, the status can be monitored using the FLASHSTA
register, or the host can wait for notification by the interrupt signal.
13.1.1. Flash Lock and Key Protection
The Flash memory is protected from errant write and erase operations by a lock and key function. Flash reads are
unrestricted. The Flash Lock and Key Register (FLASHKEY) must be written with the correct key codes, in
sequence, before each Flash write or erase operation. If a Flash write or erase operation is attempted without first
writing the correct key codes to the FLASHKEY register, Flash cannot be written or erased until the next reset.
After programming Flash, the CP2200/1 should be reset in order to protect the device from errant Flash operations.
The key codes for unlocking the CP2200/1 are 0xA5 and 0xF1. These codes must be written in sequence to the
FLASHKEY register prior to each Flash write or erase operation. Note: To ensure the integrity of Flash
contents, the on-chip VDD Monitor should not be disabled while the Flash memory is unlocked.
13.1.2. Flash Erase Procedure
Step 1: Write 0xA5 followed by 0xF1 to FLASHKEY.
Step 2: Set FLASHADDRH:FLASHADDRL to any address within the 512-byte page to be erased.
Step 3: Write the value 0x01 to FLASHERASE.
Step 4: Check FLASHSTA to determine when the Flash operation is complete. The Flash Write/Erase
Completed interrupt can also be use to determine when the operation completes.
13.1.3. Flash Write Procedure
Step 1: Write 0xA5 followed by 0xF1 to FLASHKEY.
Step 2: If the byte to be written is not 0xFF, then erase the page containing the byte.
Step 3: Set FLASHADDRH:FLASHADDRL to the address of the byte to be written.
Step 4: Write the value to be written to the FLASHDATA register.
Step 5: Check FLASHSTA to determine when the Flash operation is complete. The Flash Write/Erase
Completed interrupt can also be used to determine when the operation is complete.
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