參數(shù)資料
型號(hào): CP2201-GM
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 47/108頁(yè)
文件大?。?/td> 0K
描述: IC ETH CTRLR SNGL-CHIP 28QFN
標(biāo)準(zhǔn)包裝: 73
控制器類型: 以太網(wǎng)控制器,MAC/10Base-T
接口: 并行/串行
電源電壓: 3.1 V ~ 3.6 V
電流 - 電源: 75mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 28-QFN(5x5)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 627 (CN2011-ZH PDF)
配用: 336-1326-ND - KIT REF DESIGN PWR OVER ETHERNET
336-1316-ND - KIT EVAL FOR CP2201 ETH CTRLR
其它名稱: 336-1313
CP2200/1
Rev. 1.0
43
10. Power Modes
The CP2200/1 has four power modes that can be used to minimize overall system power consumption. The power
modes vary in device functionality and recovery methods. Each of the following power modes is explained in the
following sections:
Normal Mode (Device Fully Functional)
Link Detection Mode (Transmitter Disabled)
Memory Mode (Transmitter and Receiver Disabled)
Shutdown Mode (Oscillator Output Disabled)
The power modes above are achieved by disabling specific primary functions of the CP2200/1. Figure 15 shows
how power is distributed throughout the CP2200/1. To further reduce power consumption in any of the power
modes, secondary device functions may be turned off individually. The secondary device functions that may be
turned off are:
Link/Activity LED Drivers
Weak pull-ups to VDD
VDD Monitor
Figure 15. Power and Clock Distribution Control
VDD
System
Clock
(Oscillator)
Parallel Host
Interface
TX and RX
Buffers
MAC
Flash Memory
VDD Monitor
PHY
Transmitter
Receiver
VDMCN.7
OSCPWR.0
PHYCN.7
TXEN
(PHYCN.6)
RXEN
(PHYCN.5)
IOPWR
Activity LED
Link LED
Weak
Pullups
All Digital Pins
LINK (LA) Pin
ACT Pin
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