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參數資料
| 型號： | CP2201-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數： | 63/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ETH CTRLR SNGL-CHIP 28QFN |
| 標準包裝： | 73 |
| 控制器類型： | 以太網控制器，MAC/10Base-T |
| 接口： | 并行/串行 |
| 電源電壓： | 3.1 V ~ 3.6 V |
| 電流 - 電源： | 75mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 28-QFN（5x5） |
| 包裝： | 管件 |
| 產品目錄頁面： | 627 (CN2011-ZH PDF) |
| 配用： | 336-1326-ND - KIT REF DESIGN PWR OVER ETHERNET 336-1316-ND - KIT EVAL FOR CP2201 ETH CTRLR |
| 其它名稱： | 336-1313 |
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CP2200/1
58
Rev. 1.0
12. Receive Interface
12.1. Overview
The CP2200/1 has a 4k circular receive FIFO buffer and an 8 entry translation look-aside buffer (TLB) capable of
storing up to 8 packets at a time. Each TLB entry holds the starting address, length, and other information about a
single received packet. Once a packet is received, the host microcontroller is notified using the interrupt request
pin. The host microcontroller may then copy the contents of the packet to its local memory through the host
interface or skip the packet by writing ‘1’ to RXSKIP (RXCN.1). Skipped packets remain in memory but will be
overwritten as new packets arrive.
The receive interface has an advanced receive filter and hash table to prevent unwanted packets from reaching the
receive buffer. For all packet types not supported by the receive filter, the CP2200/1 allows the host microcontroller
complete random access to the receive buffer. The host microcontroller can check specific bytes in the packet to
determine whether or not to copy the packet.
.
Figure 17. Receive Interface Block Diagram
12.2. Reading a Packet Using the Autoread Interface
Once reset initialization is complete (Section 6.2 on page 18) and the receive buffer, filter, and hash table (Section
12.4) are initialized, the CP2200/1 is ready to receive Ethernet packets. After receiving notification of a new packet,
the following procedure can be used to read the packet:
Step 1: Read RXVALID (CPINFOH.7) and RXOK (CPINFOL.7) to check if the current packet was received
correctly. The host processor may optionally use the packet starting address CPADDR to read
specific bytes in the packet and determine whether to copy or skip the current packet. The random
access method described in Section 7.1 on page 23 can be used to access the buffer.
Step 2: If RXVALID or RXOK is 0, or to skip the packet, write a ‘1’ to RXSKIP (RXCN.1).
If RXVALID and RXOK are 1, read the length of the current packet from CPLENH:CPLENL.
Step 3: Read the entire packet, one byte at a time, by reading RXAUTORD.
Step 4: If the entire packet was read, write a ‘1’ to RXCLRV (RXCN.2).
If there are any unread bytes remaining in the current buffer, write a ‘1’ to RXSKIP (RXCN.1).
12.3. Timing and Buffer Overflow Considerations
For 10 Base-T Ethernet, a minimum-sized packet of 64 bytes is received in 51.2 us. The maximum number of
packets that can be held by the receive buffer is eight. To ensure that pointer corruption does not occur, software
should disable packet reception (RXINH = 1) after the seventh packet has arrived in the receive buffer. If the ability
to service the packet received interrupt is longer than 51.2us, then software should use the random access method
to retrieve data from the receive buffer. The random access method described in Section 7.1 on page 23.
4 KB
Receive
Buffer
with
8-entry TLB
Programmable
Receive Filter and
Hash Table
Host Interface Registers
Autoread Interface:
Autoread Data Register
Packet Skip Bit
Current Packet:
Packet Address
Packet Length
Packet Information
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