參數(shù)資料
型號(hào)： COP87L88RGV-XE
廠(chǎng)商： NATIONAL SEMICONDUCTOR CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-Bit One-Time Programmable (OTP) Microcontroller with 32 Kbytes of Program Memory
中文描述： 8-BIT, OTPROM, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 7/34頁(yè)
文件大小： 385K
代理商： COP87L88RGV-XE
Pin Descriptions
(Continued)
Port G has the following dedicated functions:
G1
WDOUT WATCHDOG and/or Clock Monitor
dedicated output
G7
CKO Oscillator dedicated output or general
purpose input
Port C is an 8-bit I/O port. The 28-pin device does not have
a full complement of Port C pins. The unavailable pins are
not terminated. A read operation for these unterminated
pins will return unpredictable values.
Port I is an 8-bit Hi-Z input port. The 28-pin device does not
have a full complement of Port I pins. The unavailable pins
are not terminated (i.e. they are floating). A read operation
from these unterminated pins will return unpredictable val-
ues. The user should ensure that the software takes this
into account by either masking out these inputs, or else re-
stricting the accesses to bit operations only. If unterminated,
Port I pins will draw power only when addressed. The I port
leakage current may be higher in 28-pin devices.
Port D is a recreated 8-bit output port that is preset high
when RESET goes low. D port recreation is one clock cycle
behind the normal port timing. The user can tie two or more
D port outputs (except D2 pin) together in order to get a
higher drive.
Functional Description
The architecture of the device is modified Harvard architec-
ture. With the Harvard architecture, the control store pro-
gram memory (ROM) is separated from the data store mem-
ory (RAM). Both ROM and RAM have their own separate
addressing space with separate address buses. The archi-
tecture, though based on Harvard architecture, permits
transfer of data from ROM to RAM.
CPU REGISTERS
The CPU can do an 8-bit addition, subtraction, logical or
shift operation in one instruction (t
c
) cycle time.
There are five CPU registers:
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.
SP is the 8-bit stack pointer, which points to the subroutine/
interrupt stack (in RAM). The SP is initialized to RAM ad-
dress 06F with reset.
All the CPU registers are memory mapped with the excep-
tion of the Accumulator (A) and the Program Counter (PC).
PROGRAM MEMORY
Program memory consists of 4 kbytes of OTP EPROM.
These bytes may hold program instructions or constant data
(data tables fortheLAIDinstruction,jumpvectorsfortheJID
instruction, and interrupt vectors for the VIS instruction).
The program memory is addressed by the 15-bit program
counter (PC). All interrupts vector to program memory loca-
tion 0FF Hex.
The device can be configured to inhibit external reads of the
program memory. This is done by programming the Security
Byte.
SECURITY FEATURE
The program memory array has an associate Security Byte
that is located outside of the program address range. This
byte can be addressed only from programming mode by a
programmer tool.
Security is an optional feature and can only be asserted
after the memory array has been programmed and verified.
A secured part will read all 00(hex) by a programmer. The
part will fail Blank Check and will fail Verify operations. A
Read operation will fill the programmer’s memory with
00(hex). The Security Byte itself is always readable with a
value of 00(hex) if unsecure and FF(hex) if secure.
DATA MEMORY
The data memory address space includes the on-chip RAM
and data registers, the I/O registers (Configuration, Data
and Pin), the control registers, the MICROWIRE/PLUS SIO
shift register, and the various registers, and counters asso-
ciated with the timers (with the exception of the IDLE timer).
Data memory is addressed directly by the instruction or indi-
rectly by the B, X and SP pointers.
The device has 128 bytes of RAM. Sixteen bytes of RAM
are mapped as ‘‘registers’’ at addresses 0F0 to 0FF Hex.
These registers can be loaded immediately, and also decre-
mented and tested with the DRSZ (decrement register and
skip if zero) instruction. The memory pointer registers X, SP,
and B are memory mapped into this space at address loca-
tions 0FC to 0FE Hex respectively, with the other registers
(other than reserved register 0FF) being available for gener-
al usage.
The instruction set permits any bit in memory to be set,
reset or tested. All I/O and registers on the device (except A
and PC) are memory mapped; therefore, I/O bits and regis-
ter bits can be directly and individually set, reset and tested.
The accumulator (A) bits can also be directly and individual-
ly tested.
Reset
The RESET input when pulled low initializes the microcon-
troller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the data and configuration
registers for Ports L, G, and C are cleared, resulting in these
Ports being initialized to the TRI-STATE mode. Pin G1 of the
G Port is an exception (as noted below) since pin G1 is
dedicated as the WATCHDOG and/or Clock Monitor error
output pin. Port D is initialized high with RESET. The PC,
PSW, CNTRL, ICNTRL, and T2CNTRL control registers are
cleared. The Multi-Input Wakeup registers WKEN, WKEDG,
and WKPND are cleared. The Stack Pointer, SP, is initial-
ized to 06F Hex.
The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed, and with both
the WATCHDOG service window bits set and the Clock
Monitor bit set. The WATCHDOG and Clock Monitor detec-
tor circuits are inhibited during reset. The WATCHDOG serv-
ice window bits are initialized to the maximum WATCHDOG
service window of 64k t
c
clock cycles. The Clock Monitor bit
is initialized high, and will cause a Clock Monitor error fol-
lowing reset if the clock has not reached the minimum spec-
ified frequency at the termination of reset. A Clock Monitor
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