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參數(shù)資料
| 型號： | COP87L88RGV-XE |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-Bit One-Time Programmable (OTP) Microcontroller with 32 Kbytes of Program Memory |
| 中文描述： | 8-BIT, OTPROM, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 13/34頁 |
| 文件大小： | 385K |
| 代理商： | COP87L88RGV-XE |
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Power Save Modes
(Continued)
If an RC clock option is being used, the fixed delay is intro-
duced optionally. A control bit, CLKDLY, mapped as config-
uration bit G7, controls whether the delay is to be intro-
duced or not. The delay is included if CLKDLY is set, and
excluded if CLKDLY is reset. The CLKDLY bit is cleared on
reset.
The WATCHDOG detector circuit is inhibited during the
HALT mode. However, the clock monitor circuit, if enabled,
remains active during HALT mode in order to ensure a clock
monitor error if the device inadvertently enters the HALT
mode as a result of a runaway program or power glitch.
IDLE MODE
The device is placed in the IDLE mode by writing a ‘‘1’’ to
the IDLE flag (G6 data bit). In this mode, all activity, except
the associated on-board oscillator circuitry, the WATCH-
DOG logic, the clock monitor and the IDLE Timer T0, is
stopped.
As with the HALT mode, the device can be returned to nor-
mal operation with a reset, or with a Multi-Input Wake-up
from the L Port. Alternately, the microcontroller resumes
normal operation from the IDLE mode when the thirteenth
bit (representing 4.096 ms at internal clock frequency of
1 MHz, t
c
e
1
m
s) of the IDLE Timer toggles.
This toggle condition of the thirteenth bit of the IDLE Timer
T0 is latched into the T0PND pending flag.
The user has the option of being interrupted with a transition
on the thirteenth bit of the IDLE Timer T0. The interrupt can
be enabled or disabled via the T0EN control bit. Setting the
T0EN flag enables the interrupt and vice versa.
The user can enter the IDLE mode with the Timer T0 inter-
rupt enabled. In this case, when the T0PND bit gets set, the
device will first execute the Timer T0 interrupt service rou-
tine and then return to the instruction following the ‘‘Enter
Idle Mode’’ instruction.
Alternatively, the user can enter the IDLE mode with the
IDLE Timer T0 interrupt disabled. In this case, the device
will resume normal operation with the instruction immediate-
ly following the ‘‘Enter IDLE Mode’’ instruction.
Note:
It is necessary to program two NOP instructions following both the
set HALT mode and set IDLE mode instructions. These NOP instruc-
tions are necessary to allow clock resynchronization following the
HALT or IDLE modes. Due to the on-board 8k EPROM with port
recreation logic, the HALT/IDLE current is much higher compared to
the equivalent masked device (COP888CL/COP884CL).
Multi-Input Wakeup
The Multi-Input Wakeup feature is used to return (wakeup)
the device from either the HALT or IDLE modes. Alternately
Multi-Input Wakeup/Interrupt feature may also be used to
generate up to 8 edge selectable external interrupts.
Figure 9 shows the Multi-Input Wakeup logic.
TL/DD/12524–12
FIGURE 9. Multi-Input Wake Up Logic
http://www.national.com
13
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