參數(shù)資料
型號(hào)： COP87L88RGV-XE
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： 8-Bit One-Time Programmable (OTP) Microcontroller with 32 Kbytes of Program Memory
中文描述： 8-BIT, OTPROM, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 17/34頁(yè)
文件大?。?/td> 385K
代理商： COP87L88RGV-XE
Interrupts
(Continued)
SOFTWARE TRAP
The Software Trap (ST) is a special kind of non-maskable
interrupt which occurs when the INTR instruction (used to
acknowledge interrupts) is fetched from ROM and placed
inside the instruction register. This may happen when the
PC is pointing beyond the available ROM address space or
when the stack is over-popped.
When an ST occurs, the user can re-initialize the stack
pointer and do a recovery procedure (similar to reset, but
not necessarily containing all of the same initialization pro-
cedures) before restarting.
The occurrence of an ST is latched into the ST pending bit.
The GIE bit is not affected and the ST pending bit
(not
accessible by the user)
is used to inhibit other interrupts
and to direct the program to the ST service routine with the
VIS instruction. The RPND instruction is used to clear the
software interrupt pending bit. This bit is also cleared on
reset.
The ST has the highest rank among all interrupts.
Nothing (except another ST) can interrupt an ST being
serviced.
WATCHDOG
The device contains a WATCHDOG and clock monitor. The
WATCHDOG is designed to detect the user program getting
stuck in infinite loops resulting in loss of program control or
‘‘runaway’’ programs. The Clock Monitor is used to detect
the absence of a clock or a very slow clock below a speci-
fied rate on the CKI pin.
The WATCHDOG consists of two independent logic blocks:
WD UPPER and WD LOWER. WD UPPER establishes the
upper limit on the service window and WD LOWER defines
the lower limit of the service window.
Servicing the WATCHDOG consists of writing a specific val-
ue to a WATCHDOG Service Register named WDSVR
which is memory mapped in the RAM. This value is com-
posed of three fields, consisting of a 2-bit Window Select, a
5-bit Key Data field, and the 1-bit Clock Monitor Select field.
Table III shows the WDSVR register.
TABLE III. WATCHDOG Service Register (WDSVR)
Window
Select
Key Data
Clock
Monitor
X
X
0
1
1
0
0
Y
7
6
5
4
3
2
1
0
The lower limit of the service window is fixed at 2048 in-
struction cycles. Bits 7 and 6 of the WDSVR register allow
the user to pick an upper limit of the service window.
Table IV shows the four possible combinations of lower and
upper limits for the WATCHDOG service window. This flexi-
bility in choosing the WATCHDOG service window prevents
any undue burden on the user software.
Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the
5-bit Key Data field. The key data is fixed at 01100. Bit 0 of
the WDSVR Register is the Clock Monitor Select bit.
TABLE IV. WATCHDOG Service Window Select
WDSVR
Bit 7
WDSVR
Bit 6
Service Window
(Lower-Upper Limits)
0
0
1
1
0
1
0
1
2k–8k t
c
Cycles
2k–16k t
c
Cycles
2k–32k t
c
Cycles
2k–64k t
c
Cycles
Clock Monitor
The Clock Monitor aboard the device can be selected or
deselected under program control. The Clock Monitor is
guaranteed not to reject the clock if the instruction cycle
clock (1/t
c
) is greater or equal to 10 kHz. This equates to a
clock input rate on CKI of greater or equal to 100 kHz.
WATCHDOG Operation
The WATCHDOG and Clock Monitor are disabled during
reset. The device comes out of reset with the WATCHDOG
armed, the WATCHDOG Window Select (bits 6, 7 of the
WDSVR Register) set, and the Clock Monitor bit (bit 0 of the
WDSVR Register) enabled. Thus, a Clock Monitor error will
occur after coming out of reset, if the instruction cycle clock
frequency has not reached a minimum specified value, in-
cluding the case where the oscillator fails to start.
The WDSVR register can be written to only once after reset
and the key data (bits 5 through 1 of the WDSVR Register)
must match to be a valid write. This write to the WDSVR
register involves two irrevocable choices: (i) the selection of
the WATCHDOG service window (ii) enabling or disabling of
the Clock Monitor. Hence, the first write to WDSVR Register
involves selecting or deselecting the Clock Monitor, select
the
WATCHDOG
service
WATCHDOG key data. Subsequent writes to the WDSVR
register will compare the value being written by the user to
the WATCHDOG service window value and the key data
(bits 7 through 1) in the WDSVR Register. Table V shows
the sequence of events that can occur.
window
and
match
the
The user must service the WATCHDOG at least once be-
fore the upper limit of the serivce window expires. The
WATCHDOG may not be serviced more than once in every
lower limit of the service window. The user may service the
WATCHDOG as many times as wished in the time period
between the lower and upper limits of the service window.
The first write to the WDSVR Register is also counted as a
WATCHDOG service.
The WATCHDOG has an output pin associated with it. This
is the WDOUT pin, on pin 1 of the port G. WDOUT is active
low. The WDOUT pin is in the high impedance state in the
inactive state. Upon triggering the WATCHDOG, the logic
will pull the WDOUT (G1) pin low for an additional
16 t
c
–32 t
c
cycles after the signal level on WDOUT pin goes
below the lower Schmitt trigger threshold. After this delay,
the device will stop forcing the WDOUT output low.
The WATCHDOG service window will restart when the
WDOUT pin goes high It is recommended that the user tie
the WDOUT pin back to V
CC
through a resistor in order to
pull WDOUT high.
A WATCHDOG service while the WDOUT signal is active
will be ignored. The state of the WDOUT pin is not guaran-
teed on reset, but if it powers up low then the WATCHDOG
will time out and WDOUT will enter high impedance state.
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17
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