參數(shù)資料
型號： COP87L88RGV-XE
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： 8-Bit One-Time Programmable (OTP) Microcontroller with 32 Kbytes of Program Memory
中文描述： 8-BIT, OTPROM, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 11/34頁
文件大?。?/td> 385K
代理商： COP87L88RGV-XE
Timers
(Continued)
TL/DD/12524–10
FIGURE 7. Timer in External Event Counter Mode
Mode 3. Input Capture Mode
The device can precisely measure external frequencies or
time external events by placing the timer block, Tx, in the
input capture mode.
In this mode, the timer Tx is constantly running at the fixed
t
c
rate. The two registers, RxA and RxB, act as capture
registers. Each register acts in conjunction with a pin. The
register RxA acts in conjunction with the TxA pin and the
register RxB acts in conjunction with the TxB pin.
The timer value gets copied over into the register when a
trigger event occurs on its corresponding pin. Control bits,
TxC3, TxC2 and TxC1, allow the trigger events to be speci-
fied either as a positive or a negative edge. The trigger con-
dition for each input pin can be specified independently.
The trigger conditions can also be programmed to generate
interrupts. The occurrence of the specified trigger condition
on the TxA and TxB pins will be respectively latched into the
pending flags, TxPNDA and TxPNDB. The control flag
TxENA allows the interrupt on TxA to be either enabled or
disabled. Setting the TxENA flag enables interrupts to be
generated when the selected trigger condition occurs on the
TxA pin. Similarly, the flag TxENB controls the interrupts
from the TxB pin.
Underflows from the timer can also be programmed to gen-
erate interrupts. Underflows are latched into the timer TxC0
pending flag (the TxC0 control bit serves as the timer under-
flow interrupt pending flag in the Input Capture mode). Con-
sequently, the TxC0 control bit should be reset when enter-
ing the Input Capture mode. The timer underflow interrupt is
enabled with the TxENA control flag. When a TxA interrupt
occurs in the Input Capture mode, the user must check both
whether a TxA input capture or a timer underflow (or both)
caused the interrupt.
Figure 8 shows a block diagram of the timer in Input Capture
mode.
TIMER CONTROL FLAGS
The timers T1 and T2 have indentical control structures.
The control bits and their functions are summarized below.
TxC0
Timer Start/Stop control in Modes 1 and 2
(Processor Independent PWM and External
Event Counter), where 1
e
Start, 0
e
Stop
Timer Underflow Interrupt Pending Flag in
Mode 3 (Input Capture)
TxPNDA Timer Interrupt Pending Flag
TxPNDB Timer Interrupt Pending Flag
TxENA
TxENB
Timer Interrupt Enable Flag
Timer Interrupt Enable Flag
1
e
Timer Interrupt Enabled
0
e
Timer Interrupt Disabled
Timer mode control
Timer mode control
Timer mode control
TxC3
TxC2
TxC1
TL/DD/12524–11
FIGURE 8. Timer in Input Capture Mode
http://www.national.com
11
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