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參數(shù)資料
| 型號(hào)： | COP87L88RGV-XE |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-Bit One-Time Programmable (OTP) Microcontroller with 32 Kbytes of Program Memory |
| 中文描述： | 8-BIT, OTPROM, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 12/34頁 |
| 文件大小： | 385K |
| 代理商： | COP87L88RGV-XE |
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Timers
(Continued)
The timer mode control bits (TxC3, TxC2 and TxC1) are detailed below:
TxC3
TxC2
TxC1
Timer Mode
Interrupt A
Source
Interrupt B
Source
Timer
Counts On
0
0
0
MODE 2 (External
Event Counter)
Timer
Underflow
Pos. TxB
Edge
TxA
Pos. Edge
0
0
1
MODE 2 (External
Event Counter)
Timer
Underflow
Pos. TxB
Edge
TxA
Neg. Edge
1
0
1
MODE 1 (PWM)
TxA Toggle
Autoreload
RA
Autoreload
RB
t
c
1
0
0
MODE 1 (PWM)
No TxA Toggle
Autoreload
RA
Autoreload
RB
t
c
0
1
0
MODE 3 (Capture)
Captures:
TxA Pos. Edge
TxB Pos. Edge
Pos. TxA
Edge or
Timer
Underflow
Pos. TxB
Edge
t
c
1
1
0
MODE 3 (Capture)
Captures:
TxA Pos. Edge
TxB Neg. Edge
Pos. TxA
Edge or
Timer
Underflow
Neg. TxB
Edge
t
c
0
1
1
MODE 3 (Capture)
Captures:
TxA Neg. Edge
TxB Pos. Edge
Neg. TxA
Edge or
Timer
Underflow
Pos. TxB
Edge
t
c
1
1
1
MODE 3 (Capture)
Captures:
TxA Neg. Edge
TxB Neg. Edge
Neg. TxA
Edge or
Timer
Underflow
Neg. TxB
Edge
t
c
Power Save Modes
The device offers the user two power save modes of opera-
tion: HALT and IDLE. In the HALT mode, all microcontroller
activities are stopped. In the IDLE mode, the on-board oscil-
lator circuitry and timer T0 are active but all other microcon-
troller activities are stopped. In either mode, all on-board
RAM, registers, I/O states, and timers (with the exception of
T0) are unaltered.
HALT MODE
The device is placed in the HALT mode by writing a ‘‘1’’ to
the HALT flag (G7 data bit). All microcontroller activities,
including the clock, timers, are stopped. The WATCHDOG
logic is disabled during the HALT mode. However, the clock
monitor circuitry, if enabled, remains active and will cause
the WATCHDOG output pin (WDOUT) to go low. If the
HALT mode is used and the user does not want to activate
the WDOUT pin, the Clock Monitor should be disabled after
the device comes out of reset (resetting the Clock Monitor
control bit with the first write to the WDSVR register). In the
HALT mode, the power requirements are minimal and the
applied voltage (V
CC
) may be decreased to Vr (Vr
e
2.0V)
without altering the state of the machine.
The device supports three different ways of exiting the
HALT mode. The first method of exiting the HALT mode is
with the Multi-Input Wakeup feature on the L port. The sec-
ond method is with a low to high transition on the CKO (G7)
pin. This method precludes the use of the crystal clock con-
figuration (since CKO becomes a dedicated output), and so
may be used with an RC clock configuration. The third
method of exiting the HALT mode is by pulling the RESET
pin low.
Since a crystal or ceramic resonator may be selected as the
oscillator, the Wakeup signal is not allowed to start the chip
running immediately since crystal oscillators and ceramic
resonators have a delayed start up time to reach full ampli-
tude and frequency stability. The IDLE timer is used to gen-
erate a fixed delay to ensure that the oscillator has indeed
stabilized before allowing instruction execution. In this case,
upon detecting a valid Wakeup signal, only the oscillator
circuitry is enabled. The IDLE timer is loaded with a value of
256 and is clocked with the t
c
instruction cycle clock. The t
c
clock is derived by dividing the oscillator clock down by a
factor of 10. The Schmitt trigger following the CKI inverter
on the chip ensures that the IDLE timer is clocked only
when the oscillator has a sufficiently large amplitude to
meet the Schmitt trigger specifications. This Schmitt trigger
is not part of the oscillator closed loop. The startup timeout
from the IDLE timer enables the clock signals to be routed
to the rest of the chip.
http://www.national.com
12
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