
Instruction Set
(Continued)
INSTRUCTION SET
ADD
ADC
A,Meml
A,Meml
ADD
ADD with Carry
A
w
A
a
Meml
A
w
A
a
Meml
a
C, C
w
Carry,
HC
w
Half Carry
A
w
A
b
MemI
a
C, C
w
Carry,
HC
w
Half Carry
A
w
A and Meml
Skip next if (A and Imm)
e
0
A
A or Meml
A
w
A xor Meml
Compare MD and Imm, Do next if MD
e
Imm
Compare A and Meml, Do next if A
e
Meml
Compare A and Meml, Do next if A
i
Meml
Compare A and Meml, Do next if A
l
Meml
Do next if lower 4 bits of B
i
Imm
Reg
Reg
b
1, Skip if Reg
e
0
1 to bit, Mem (bit
e
0 to 7 immediate)
0 to bit, Mem
If bit in A or Mem is true do next instruction
Reset Software Interrupt Pending Flag
A
Y
Mem
A
Y
[
X
]
A
w
Meml
A
w
[
X
]
B
w
Mem
w
Imm
Reg
w
Imm
A
Y
[
B
]
, (B
w
B
g
1)
A
Y
[
X
]
, (X
w
g
1)
A
w
[
B
]
, (B
w
B
g
1)
A
w
[
X
]
, (X
w
g
1)
[
B
]
w
Imm, (B
w
g
1)
A
w
0
A
w
A
a
1
A
w
A
b
1
A
w
ROM (PU,A)
A
w
BCD correction of A (follows ADC, SUBC)
C
Y
A7
A0
C
C
w
A7
w
. . .
w
A0
w
C
A7 . . . A4
Y
A3 . . . A0
C
1, HC
w
1
C
w
0, HC
w
0
IF C is true, do next instruction
If C is not true, do next instruction
SP
SP
a
1, A
[
SP
]
[
SP
]
w
A, SP
SP
b
1
PU
w
[
VU
]
, PL
w
[
VL
]
PC
w
ii (ii
15 bits, 0 to 32k)
PC9 . . . 0
w
i (i
e
12 bits)
PC
PC
a
r (r is
b
a
32, except 1)
[
SP
]
w
PL,
[
SP
b
1
]
w
PU,SP
b
2, PC
ii
[
SP
]
w
PL,
[
SP
b
1
]
w
PU,SP
b
2, PC9 . . . 0
w
i
PL
w
ROM (PU,A)
SP
a
2, PL
[
SP
]
, PU
w
[
SP
b
1
]
SP
a
2, PL
w
[
SP
]
,PU
w
[
SP
b
1
]
SP
a
w
[
SP
]
,PU
w
[
SP
b
1
]
,GIE
w
1
[
SP
]
w
PL,
[
SP
b
1
]
w
PU, SP
b
2, PC
w
0FF
PC
w
PC
a
1
SUBC
A,Meml
Subtract with Carry
AND
ANDSZ
OR
XOR
IFEQ
IFEQ
IFNE
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
RPND
A,Meml
A,Imm
A,Meml
A,Meml
MD,Imm
A,Meml
A,Meml
A,Meml
Y
Reg
Y
,Mem
Y
,Mem
Y
,Mem
Logical AND
Logical AND Immed., Skip if Zero
Logical OR
Logical EXclusive OR
IF EQual
IF EQual
IF Not Equal
IF Greater Than
If B Not Equal
Decrement Reg., Skip if Zero
Set BIT
Reset BIT
IF BIT
Reset PeNDing Flag
X
X
LD
LD
LD
LD
LD
A,Mem
A,
[
X
]
A,Meml
A,
[
X
]
B,Imm
Mem,Imm
Reg,Imm
A,
[
B
g
]
A,
[
X
g
]
A,
[
B
g
]
A,
[
X
g
]
[
B
g
]
,Imm
EXchange A with Memory
EXchange A with Memory
[
X
]
LoaD A with Memory
LoaD A with Memory
[
X
]
LoaD B with Immed.
LoaD Memory Immed.
LoaD Register Memory Immed.
EXchange A with Memory
[
B
]
EXchange A with Memory
[
X
]
LoaD A with Memory
[
B
]
LoaD A with Memory
[
X
]
LoaD Memory
[
B
]
Immed.
X
X
LD
LD
LD
CLR
INC
DEC
LAID
DCOR
RRC
RLC
SWAP
SC
RC
IFC
IFNC
POP
PUSH
A
A
A
CLeaR A
INCrement A
DECrementA
Load A InDirect from ROM
Decimal CORrect A
Rotate A Right thru C
Rotate A Left thru C
SWAP nibbles of A
Set C
Reset C
IF C
IF Not C
POP the stack into A
PUSH A onto the stack
A
A
A
A
A
A
VIS
JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP
Vector to Interrupt Service Routine
Jump absolute Long
Jump absolute
Jump relative short
Jump SubRoutine Long
Jump SubRoutine
Jump InDirect
RETurn from subroutine
RETurn and SKip
RETurn from Interrupt
Generate an Interrupt
No OPeration
Addr.
Addr.
Disp.
Addr.
Addr.
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