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參數(shù)資料
| 型號(hào)： | COP404C |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | COP404C ROMless CMOS Microcontrollers |
| 中文描述： | COP404C無ROM的CMOS微控制器 |
| 文件頁數(shù)： | 7/18頁 |
| 文件大小： | 345K |
| 代理商： | COP404C |
Functional Description
(Continued)
4. All successive transfer of control instructions and suc-
cessive LBIs have been completed (e.g. if the main
program is executing a JP instruction which transfers
program control to another JP instruction, the interrupt
will not be acknowledged until the second JP instruc-
tion has been executed).
c. Upon acknowledgement of an interrupt, the skip logic
status is saved and later restored upon popping of the
stack. For example, if an interrupt occurs during the exe-
cution of an ASC (Add with Carry, Skip on Carry) instruc-
tion which results in carry, the skip logic status is saved
and program control is transferred to the interrupt servic-
ing routine at hex address 0FF. At the end of the interrupt
routine, a RET instruction is executed to pop the stack
and return program control to the instruction following the
original ASC. At this time, the skip logic is enabled and
skips this instruction because of the previous ASC carry.
Subroutines should not be nested within the interrupt
service routine, since their popping of the stack will en-
able any previously saved main program skips, interfering
with the orderly execution of the interrupt routine.
d. The instruction at hex address 0FF must be a NOP.
e. An LEI instruction may be put immediately before the
RET instruction to re-enable interrupts.
MICROBUS INTERFACE
With MB pin tied to Ground, the COP404C can be used as a
peripheral microprocessor device, inputting and outputting
data from and to a host microprocessor (
m
P). IN1, IN2 and
IN3 general purpose inputs become MICROBUS compatible
read-strobe, chip-select, and write-strobe lines, respectively.
IN1 becomes RD D a logic ‘‘0’’ on this input will cause Q
latch data to be enabled to the L ports for input to the
m
P.
IN2 becomes CS D a logic ‘‘0’’ on this line selects the
COP404C and the
m
P peripheral device by enabling the op-
eration of the RD and WR lines and allows for the selection
of one of several peripheral components. IN3 becomes WR
D a logic ‘‘0’’ on this line will write bus data from the L ports
to the Q latches for input to the COP404C. G0 becomes
INTR a ‘‘ready’’ output, reset by a write pulse from the
m
P
on the WR line, providing the ‘‘handshaking’’ capability nec-
essary for asynchronous data transfer between the host
CPU and the COP404C.
This option has been designed for compatibility with Nation-
al’s MICROBUS - a standard interconnect system for 8-bit
parallel data transfer between MOS/LSI CPUs and interfac-
ing devices. (See MICROBUS National Publication). The
TL/DD/5530–7
FIGURE 6. MICROBUS Option Interconnect
functioning and timing relationships between the signal lines
affected by this option are as specified for the MICROBUS
interface, and are given in the AC electrical characteristics
and shown in the timing diagrams (Figures 4 and 5). Con-
nection of the COP404C to the MICROBUS is shown inFig-
ure 6.
INITIALIZATION
The external RC network shown in Figure 7 must be con-
nected to the RESET pin for the internal reset logic to initial-
ize the device upon power-up. The RESET pin is configured
as a Schmitt trigger input. If not used, it should be connect-
ed to V
CC
. Initialization will occur whenever a logic ‘‘0’’ is
applied to the RESET input, providing it stays low for at
least three instruction cycle times.
Upon initialization, the PC register is cleared to 0 (ROM ad-
dress 0) and the A, B, C, D, EN, IL, T and G registers are
cleared. The SKL latch is set, thus enabling SK as a clock
output. Data Memory (RAM) is not cleared upon initializa-
tion. The first instruction at address 0 must be a CLRA
(clear A register).
TL/DD/5530–8
FIGURE 7. Power-Up Circuit
TIMER
The timer is operated as a time-base counter. The instruc-
tion cycle frequency generated from CKI passes through a
2-bit divide-by-4 prescaler. The output of this prescaler in-
crements the 8-bit T counter thus providing a 10-bit timer.
The prescaler is cleared during execution of a CAMT in-
struction and on reset. For example, using a 1MHz crystal,
the instruction cycle frequency of 250 kHz (divide by 4) in-
crements the 10-bit timer every 4
m
S. By presetting the
counter and detecting overflow, accurate timeouts between
16
m
S (4 counts) and 4.096 mS (1024 counts) are possible.
Longer timeouts can be achieved by accumulating, under
software control, multiple overflows.
HALT MODE
The COP404C is a FULLY STATIC circuit; therefore, the
user may stop the system oscillator at any time to halt the
chip. The chip may also be halted by two other ways (see
Figure 8):
D Software HALT: by using the HALT instruction.
D Hardware HALT: by using the HALT I/O port CKOH. It
is an I/O flip-flop which is an indicator of the HALT
status. An external signal can over-ride this pin to start
and stop the chip. By forcing CKOH high the
7
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| COP404LSN-5 | COP404LSN-5 ROMLESS N-CHANNEL MICROCONTROLLERS |
| COP404CN | COP404C ROMless CMOS Microcontrollers |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| COP404CN | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:COP404C ROMless CMOS Microcontrollers |
| COP404LSN-5 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:COP404LSN-5 ROMLESS N-CHANNEL MICROCONTROLLERS |
| COP404N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-Bit Microcontroller |
| COP410C | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Single-Chip CMOS Microcontrollers |
| COP410C-XXX/D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-Bit Microcontroller |
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