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參數(shù)資料
| 型號： | COP404C |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | COP404C ROMless CMOS Microcontrollers |
| 中文描述： | COP404C無ROM的CMOS微控制器 |
| 文件頁數(shù)： | 3/18頁 |
| 文件大?。?/td> | 345K |
| 代理商： | COP404C |
COP404C
AC Electrical Characteristics
0
§
C
s
T
A
s
70
§
C unless otherwise specified
Parameter
Instruction Cycle
Time (t
c
)
Operating CKI
Frequency
Duty Cycle (Note 4)
Rise Time (Note 4)
Fall Time (Note 4)
Instruction Cycle
Time using D0 as a
RC Oscillator Dual-
Clock Input (Note 4)
INPUTS: (SeeFig. 3)
t
SETUP
Conditions
Min
4
16
DC
DC
40
Max
DC
DC
1.0
250
60
60
40
Units
m
s
m
s
MHz
kHz
%
ns
ns
V
t
4.5V
4.5V
l
V
CC
t
2.4V
V
CC
t
4.5V
4.5V
l
V
CC
t
2.4V
f
1
e
4 MHz
f
1
e
4 MHz external clock
R
e
30k, V
CC
e
5V
C
e
82 pF
8
16
m
s
G Inputs
SI Input
IP Input
T
c
/4
a
.7
0.3
1.0
1.7
0.25
1.0
m
s
m
s
m
s
m
s
m
s
m
s
V
CC
t
4.5V
All Others
*
V
t
4.5V
4.5V
l
V
CC
t
2.4V
t
HOLD
OUTPUT
PROPAGATION DELAY
IP7±IP0, A10±A8, SKIP
t
PD1
, t
PD0
V
OUT
e
1.5V, C
L
e
100 pF, R
L
e
5K
V
t
4.5V
4.5V
l
V
CC
t
2.4V
1.94
7.75
m
s
m
s
AD/DATA
t
PD1
, t
PD0
V
CC
t
4.5V
4.5V
l
V
CC
t
2.4V
375
1.5
ns
m
s
ALL OTHER OUTPUTS
t
PD1
, t
PD0
V
l
4.5V
4.5V
l
V
CC
t
2.4V
C
L
e
50 pF, V
CC
e
5V
g
5%
1.0
4.0
m
s
m
s
MICROBUS TIMING
Read Operation (Fig. 4)
Chip select stable before RD
b
t
CSR
Chip select hold time for RD
b
t
RCS
RD pulse width
b
t
RR
Data delay from RD
b
t
RD
RD to data floating
b
t
DF
(Note 4)
Write Operation (Fig. 5)
Chip select stable before WR
b
t
CSW
Chip select hold time for WR
b
t
WCS
WR pulse width
b
t
WW
Data set-up time for WR
b
t
DW
Data hold time for WR
b
t
WD
INTR transition time from WR
b
t
WI
65
20
400
ns
ns
ns
ns
ns
375
250
65
20
400
320
100
ns
ns
ns
ns
ns
ns
700
Note 1:
Supply current is measured after running for 2000 cycle times with a square-wave clock on CKI and all other pins pulled up to V
CC
with 20k resistors. See
current drain equation on page 16.
Note 2:
Test conditions: All inputs tied to V
CC
; L lines in TRI-STATE mode and tied to Ground; all outputs tied to Ground.
Note 3:
When forcing HALT, current is only needed for a short time (approx. 200 ns) to flip the HALT flip-flop.
Note 4:
This parameter is only sampled and not 100% tested. Variation due to the device included.
Note 5:
Voltage change must be less than 0.1 V
CC
in a 1 ms period.
Note 6:
SO output sink current must be limited to keep V
OL
less than 0.2 V
CC
to prevent entering test mode.
Note 7:
MB, TIN, DUAL, SEL10, SEL20, input levels at V
CC
or V
SS
.
3
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| COP404LSN-5 | COP404LSN-5 ROMLESS N-CHANNEL MICROCONTROLLERS |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| COP404CN | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:COP404C ROMless CMOS Microcontrollers |
| COP404LSN-5 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:COP404LSN-5 ROMLESS N-CHANNEL MICROCONTROLLERS |
| COP404N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-Bit Microcontroller |
| COP410C | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Single-Chip CMOS Microcontrollers |
| COP410C-XXX/D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-Bit Microcontroller |
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