- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379928 > COP404C (National Semiconductor Corporation) COP404C ROMless CMOS Microcontrollers PDF資料下載
參數(shù)資料
| 型號： | COP404C |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | COP404C ROMless CMOS Microcontrollers |
| 中文描述： | COP404C無ROM的CMOS微控制器 |
| 文件頁數(shù)： | 13/18頁 |
| 文件大小： | 345K |
| 代理商： | COP404C |
Instruction Set
(Continued)
TABLE III. COP404C Instruction Set
(Continued)
Machine
Language
Code
(Binary)
Mnemonic
Operand
Hex
Code
Data Flow
Skip
Conditions
Description
INPUT/OUTPUT INSTRUCTIONS
ING
33
2A
33
28
33
29
33
2E
33
3E
33
5
b
33
3A
4F
l
0011
l
0011
l
l
0010
l
1010
l
l
0011
l
0011
l
l
0010
l
1000
l
l
0011
l
0011
l
l
0010
l
1001
l
l
0011
l
0011
l
l
0010
l
1110
l
l
0011
l
0011
l
l
0011
l
1110
l
l
0011
l
0011
l
l
0101
l
y
l
l
0011
l
0011
l
l
0011
l
1010
l
l
0100
l
1111
l
G
x
A
None
Input G Ports to A
ININ
IN
x
A
None
Input IN Inputs to A
INIL
IL
3
, CKO, ‘‘0’’, IL
0
x
A
None
Input IL Latches to A
(Note 2)
Input L Ports to RAM,A
INL
L
7:4
x
RAM(B)
L
3:0
x
A
Bd
x
D
None
OBD
None
Output Bd to D Outputs
OGI
y
y
x
G
None
Output to G Ports
Immediate
Output RAM to G Ports
OMG
RAM(B)
x
G
None
XAS
A
Y
SIO, C
x
SKL
None
Exchange A with SIO
(Note 2)
Note 1:
All subscripts for alphabetical symbols indicate bit numbers unless explicitly defined (e.g., Br and Bd are explicitly defined). Bits are numbered O to N where
O signifies the least significant bit (low-order, right-most bit). For example, A
3
indicates the most significant (left-most) bit of the 4-bit A register.
Note 2:
For additional information on the operation of the XAS, JID, LQID, INIL, and SKT instructions, see below.
Note 3:
The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2 or 3. The JP instruction,
otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last word of a page.
Note 4:
A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of P). A JSRP may not be used when in pages 2 or 3. JSRP
may not jump to the last word in page 2.
Note 5:
LBI is a single-byte instruction if d
e
0, 9, 10, 11, 12, 13, 14, or 15. The machine code for the lower 4 bits equals the binary value of the ‘‘d’’ data minus 1,
e.g., to load the lower four bits of B(Bd) with the value 9 (1001
2
), the lower 4 bits of the LBI instruction equal 8 (1000
2
). To load 0, the lower 4 bits of the LBI
instruction should equal 15 (1111
2
).
Note 6:
Machine code for operand field y for LEI instruction should equal the binary value to be latched into EN, where a ‘‘1’’ or ‘‘0’’ in each bit of EN corresponds
with the selection or deselection of a particular function associated with each bit. (See Functional Description, EN Register.)
Note 7:
If SEL2O
e
1, A
Y
Br (0
x
A3)
If SEL2O
e
0, A
Y
Br (0,0
x
A3, A2).
Description of Selected Instructions
XAS INSTRUCTION
XAS (Exchange A with SIO) copies C to the SKL latch and
exchanges the accumulator with the 4-bit contents of the
SIO register. The contents of SIO will contain serial-in/seri-
al-out shift register or binary counter data, depending on the
value of the EN register. If SIO is selected as a shift register,
an XAS instruction can be performed once every 4 instruc-
tion cycles to effect a continuous data stream.
LQID INSTRUCTION
LQID (Load Q Indirect) loads the 8-bit Q register with the
contents of ROM pointed to by the 11-bit word PC10: PC8,
A, M. LQID can be used for table lookup or code conversion
such as BCD to seven-segment. The LQID instruction
‘‘pushes’’ the stack (PC
a
1
SA
SB
SC) and
replaces the least significant 8 bits of the PC as follows: A
PC (7:4), RAM(B)
PC(3:0), leaving PC(10), PC(9)
and PC(8) unchanged. The ROM data pointed to by the
new address is fetched and loaded into the Q latches. Next,
the stack is ‘‘popped’’ (SC
SB
SA
PC), re-
storing the saved value of PC to continue sequential pro-
gram execution. Since LQID pushes SB
SC, the previ-
ous contents of SC are lost.
Note: LQID uses 2 instruction cycles if executed, one if
skipped.
JID INSTRUCTION
JID (Jump Indirect) is an indirect addressing instruction,
transferring program control to a new ROM location pointed
to indirectly by A and M. It loads the lower 8 bits of the ROM
address register PC with the contents of ROM addressed by
the 11-bit word, PC10: 8, A, M. PC10, PC9 and PC8 are not
affected by JID.
Note: JID uses 2 instruction cycles if executed, one if
skipped.
13
相關PDF資料 |
PDF描述 |
|---|---|
| COP404LSN-5 | COP404LSN-5 ROMLESS N-CHANNEL MICROCONTROLLERS |
| COP404CN | COP404C ROMless CMOS Microcontrollers |
| COP410C | Single-Chip CMOS Microcontrollers |
| COP411C | Single-Chip CMOS Microcontrollers |
| COP310C | Single-Chip CMOS Microcontrollers |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| COP404CN | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:COP404C ROMless CMOS Microcontrollers |
| COP404LSN-5 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:COP404LSN-5 ROMLESS N-CHANNEL MICROCONTROLLERS |
| COP404N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-Bit Microcontroller |
| COP410C | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Single-Chip CMOS Microcontrollers |
| COP410C-XXX/D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-Bit Microcontroller |
發(fā)布緊急采購，3分鐘左右您將得到回復。