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參數(shù)資料
| 型號(hào)： | COP404C |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | COP404C ROMless CMOS Microcontrollers |
| 中文描述： | COP404C無(wú)ROM的CMOS微控制器 |
| 文件頁(yè)數(shù)： | 6/18頁(yè) |
| 文件大?。?/td> | 345K |
| 代理商： | COP404C |
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Functional Description
INTERNAL LOGIC
The processor contains its own 4-bit A register (accumula-
tor) which is the source and destination register for most
I/O, arithmetic, logic, and data memory access operations.
It can also be used to load the B
r
and B
d
portions of the B
register, to load and input 4 bits of the 8-bit Q latch or T
counter, L I/O ports data, to input 4-bit G, or IN ports, and to
perform data exchanges with the SIO register.
A 4-bit adder performs the arithmetic and logic functions,
storing the results in A. It also outputs a carry bit to the 1-bit
C register, most often employed to indicate arithmetic over-
flow. The C register in conjunction with the XAS instruction
and the EN register, also serves to control the SK output.
The 8-bit T counter is a binary up counter which can be
loaded to and from M and A using CAMT and CTMA instruc-
tions. This counter is operated as a time-base counter.
When the T counter overflows, an overflow flag will be set
(see SKT and IT instructions below). The T counter is
cleared on reset. A functional block diagram of the timer/
counter is illustrated in Figure 10a.
Four general-purpose inputs, IN3–IN0, are provided. IN1,
IN2 and IN3 may be selected (by pulling MB pin low) as
Read Strobe, Chip Select, and Write Strobe inputs, respec-
tively, for use in MICROBUS application.
The D register provides 4 general-purpose outputs and is
used as the destination register for the 4-bit contents of B
d
.
In the dual clock mode, D0 latch controls the clock selection
(see dual oscillator below).
The G register contents are outputs to a 4-bit general-pur-
pose bidirectional I/O port. G0 may be selected as an out-
put for MICROBUS applications.
The Q register is an internal, latched, 8-bit register, used to
hold data loaded to or from M and A, as well as 8-bit data
from ROM. Its contents are outputted to the L I/O ports
when the L drivers are enabled under program control. With
the MICROBUS option selected, Q can also be loaded with
the 8-bit contents of the L I/O ports upon the occurrence of
a write strobe from the host CPU.
The 8 L drivers, when enabled, output the contents of
latched Q data to the L I/O port. Also, the contents of L may
be read directly into A and M. As explained above, the MI-
CROBUS option allows L I/O port data to be latched into
the Q register.
The SIO register functions as a 4-bit serial-in/serial-out shift
register for MICROWIRE
TM
I/O and COPS peripherals, or
as a binary counter (depending on the contents of the EN
register). Its contents can be exchanged with A.
The XAS instruction copies C into the SKL latch. In the
counter mode, SK is the output SKL; in the shift register
mode, SK outputs SKL ANDed with the clock.
EN is an internal 4-bit register loaded by the LEI instruction.
The state of each bit of this register selects or deselects the
particular feature associated with each bit of the EN regis-
ter:
0. The least significant bit of the enable register, EN0, se-
lects the SIO register as either a 4-bit shift register or a 4-
bit binary counter. With EN0 set, SIO is an asynchronous
binary counter, decrementing its value by one upon each
low-going pulse (‘‘1’’ to ‘‘0’’) occurring on the SI input.
Each pulse must be at least two instruction cycles wide.
SK outputs the value of SKL. The SO output equals the
value of EN3. With EN0 reset, SIO is a serial shift register
left shifting 1 bit each instruction cycle time. The data
present at SI goes into the least significant bit of SIO. SO
can be enabled to output the most significant bit of SIO
each cycle time. The SK outputs SKL ANDed with the
instruction cycle clock.
1. With EN1 set, interrupt is enabled. Immediately following
an interrupt, EN1 is reset to disable further interrupts.
2. With EN2 set, the L drivers are enabled to output the data
in Q to the L I/O port. Resetting EN2 disables the L driv-
ers, placing the L I/O port in a high-impedance input
state.
3. EN3, in conjunction with EN0, affects the SO output. With
EN0 set (binary counter option selected) SO will output
the value loaded into EN3. With EN0 reset (serial shift
register option selected), setting EN3 enables SO as the
output of the SIO shift register, outputting serial shifted
data each instruction time. Resetting EN3 with the serial
shift register option selected disables SO as the shift reg-
ister output; data continues to be shifted through SIO and
can be exchanged with A via an XAS instruction but SO
remains set to ‘‘0’’.
INTERRUPT
The following features are associated with interrupt proce-
dure and protocol and must be considered by the program-
mer when utilizing interrupts.
a. The interrupt, once recognized as explained below,
pushes the next sequential program counter address
(PC
a
1) onto the stack. Any previous contents at the bot-
tom of the stack are lost. The program counter is set to
hex address 0FF (the last word of page 3) and EN1 is
reset.
b. An interrupt will be recognized only on the following con-
ditions:
1. EN1 has been set.
2. A low-going pulse (‘‘1’’ to ‘‘0’’) at least two instruction
cycles wide has occurred on the IN1 input.
3. A currently executing instruction has been completed.
TABLE I. ENABLE REGISTER MODES D BITS EN0 AND EN3
EN0
EN3
SIO
SI
SO
SK
0
0
Shift Register
Input to Shift
Register
Input to Shift
Register
Input to Counter
Input to Counter
0
If SKL
e
1, SK
e
clock
If SKL
e
0, SK
e
0
If SKL
e
1, SK
e
clock
If SKL
e
0, SK
e
0
SK
e
SKL
SK
e
SKL
0
1
Shift Register
Serial
out
0
1
1
1
0
1
Binary Counter
Binary Counter
6
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| COP404LSN-5 | COP404LSN-5 ROMLESS N-CHANNEL MICROCONTROLLERS |
| COP404CN | COP404C ROMless CMOS Microcontrollers |
| COP410C | Single-Chip CMOS Microcontrollers |
| COP411C | Single-Chip CMOS Microcontrollers |
| COP310C | Single-Chip CMOS Microcontrollers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| COP404CN | 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:COP404C ROMless CMOS Microcontrollers |
| COP404LSN-5 | 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:COP404LSN-5 ROMLESS N-CHANNEL MICROCONTROLLERS |
| COP404N | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:4-Bit Microcontroller |
| COP410C | 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:Single-Chip CMOS Microcontrollers |
| COP410C-XXX/D | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:4-Bit Microcontroller |
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