- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379928 > COP404C (National Semiconductor Corporation) COP404C ROMless CMOS Microcontrollers PDF資料下載
參數(shù)資料
| 型號： | COP404C |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | COP404C ROMless CMOS Microcontrollers |
| 中文描述： | COP404C無ROM的CMOS微控制器 |
| 文件頁數(shù)： | 10/18頁 |
| 文件大?。?/td> | 345K |
| 代理商： | COP404C |
External Memory Interface
The COP404C is designed for use with an external Program
Memory.
This memory may be implemented using any devices having
the following characteristics:
1. random addressing
2. LSTTL or CMOS-compatible TRI-STATE outputs
3. LSTTL or CMOS-compatible inputs
4. access time
e
1. 0
m
s max.
Typically, these requirements are met using bipolar PROMs
or MOS/CMOS PROMs, EPROMs or E
2
PROMs.
During operation, the address of the next instruction is sent
out on A10, A9, A8 and IP7 through IP0 during the time that
AD/DATA is high (logic ‘‘1’’
e
address mode). Address data
on the IP lines is stored into an external latch on the high-to-
low transition of the AD/DATA line; A10, A9 and A8 are
dedicated address outputs, and do not need to be latched.
When AD/DATA is low (logic ‘‘0’’
e
data mode), the output
of the memory is gated onto IP7 through IP0, forming the
input bus. Note that AD/DATA output has a period of one
instruction time, a duty cycle of approximately 50%, and
specifies whether the IP lines are used for address output or
data input. A simplified block diagram of the external memo-
ry interface is shown in Figure 11.
TL/DD/5530–13
FIGURE 11. External Memory Interface to COP404C
COP404C Instruction Set
Table II is a symbol table providing internal architecture, in-
struction operand and operation symbols used in the in-
struction set table.
Table III provides the mnemonic, operand, machine code
data flow, skip conditions and description of each instruc-
tion.
Table II. Instruction Set Table Symbols
Symbol
Definition
Internal Architecture Symbols
A
4-bit Accumulator
B
7-bit RAM address register
Br
Upper 3 bits of B (register address)
Bd
Lower 4 bits of B (digit address)
C
1-bit Carry register
D
4-bit Data output port
EN
4-bit Enable register
G
4-bit General purpose I/O port
IL
two 1-bit (IN0 and IN3) latches
IN
4-bit input port
L
8-bit TRI-STATE I/O port
M
4-bit contents of RAM addressed by B
PC
11-bit ROM address program counter
Q
8-bit latch for L port
SA
11-bit Subroutine Save Register A
SB
11-bit Subroutine Save Register B
SC
11-bit Subroutine Save Register C
SIO
4-bit Shift register and counter
SK
Logic-controlled clock output
SKL
1-bit latch for SK output
T
8-bit timer
Instruction operand symbols
d
4-bit operand field, 0–15 binary (RAM digit select)
r
3-bit operand field, 0–7 binary (RAM register select)
a
11-bit operand field, 0–2047
y
4-bit operand field, 0–15 (immediate data)
RAM(x) RAM addressed by variable x
ROM(x) ROM addressed by variable x
Operational Symbols
a
Plus
b
Minus
–
l
Replaces
k
–
l
is exchanged with
e
Is equal to
b
A
one’s complement of A
exclusive-or
:
range of values
Z
10
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| COP404LSN-5 | COP404LSN-5 ROMLESS N-CHANNEL MICROCONTROLLERS |
| COP404CN | COP404C ROMless CMOS Microcontrollers |
| COP410C | Single-Chip CMOS Microcontrollers |
| COP411C | Single-Chip CMOS Microcontrollers |
| COP310C | Single-Chip CMOS Microcontrollers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| COP404CN | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:COP404C ROMless CMOS Microcontrollers |
| COP404LSN-5 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:COP404LSN-5 ROMLESS N-CHANNEL MICROCONTROLLERS |
| COP404N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-Bit Microcontroller |
| COP410C | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Single-Chip CMOS Microcontrollers |
| COP410C-XXX/D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-Bit Microcontroller |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。