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參數(shù)資料
| 型號： | COP404C |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | COP404C ROMless CMOS Microcontrollers |
| 中文描述： | COP404C無ROM的CMOS微控制器 |
| 文件頁數(shù)： | 4/18頁 |
| 文件大?。?/td> | 345K |
| 代理商： | COP404C |
Connection Diagram
Dual-In-Line Package
TL/DD/5530–2
Order Number COP404CN
See NS Package Number N48A
Pin Descriptions
Pin
Description
V
CC
V
SS
CKI
RS
CKOI
L0±L7
G0±G3
D1±D3
D0
Most positive voltage
Ground
Clock input
Reset input
General purpose input
8 TRI-STATE I/O
4 general purpose I/O
3 general purpose outputs
Either general purpose output
or Dual-Clock RC input
4 general purpose inputs
Serial data output
Serial data input
Serial data clock output
I/O for ROM address and data
3 address outputs
Skip status output
Clock output
MICROBUS select input
Halt I/O pin
Dual-Clock select input
Timer input select pin (should be
connected to GND)
COP410C emulation select input
COP424C emulation select input
Ground
IN0±IN3
SO
SI
SK
IP0±IP7
A8, A9, A10
SKIP
AD/DATA
MB
CKOH
DUAL
TIN
SEL10
SEL20
UNUSED
FIGURE 2
The internal architecture is shown in Figure 1. Data paths
are illustrated in simplified form to depict how the various
logic elements communicate with each other in implement-
ing the instruction set of the device. Positive logic is used.
When a bit is set, it is a logic ‘‘1’’, when a bit is reset, it is a
logic ‘‘0’’.
PROGRAM MEMORY
Program Memory consists of a 2048-byte external memory
(typically PROM). Words of this memory may be program
instructions, constants or ROM addressing data.
ROM addressing is accomplished by a 11-bit PC register
which selects one of the 8-bit words contained in ROM. A
new address is loaded into the PC register during each in-
struction cycle. Unless the instruction is a transfer of control
instruction, the PC register is loaded with the next sequen-
tial 11-bit binary count value.
Three levels of subroutine nesting are implemented by a
three level deep stack. Each subroutine call or interrupt
pushes the next PC address into the stack. Each return
pops the stack back into the PC register.
DATA MEMORY
Data memory consists of a 512-bit RAM, organized as 8
data registers of 16
c
4-bit digits. RAM addressing is imple-
mented by a 7-bit B register whose upper 3 bits (B
r
) select 1
of 8 data registers and lower 4 bits (B
d
) select 1 of 16 4-bit
digits in the selected data register. While the 4-bit contents
of the selected RAM digit (M) are usually loaded into or
from, or exchanged with, the A register (accumulator), it
may also be loaded into or from the Q latches or T counter
or loaded from the L ports. RAM addressing may also be
performed directly by the LDD and XAD instructions based
upon the immediate operand field of these instructions. The
B
d
register also serves as a source register for 4-bit data
sent directly to the D outputs.
4
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| COP404LSN-5 | COP404LSN-5 ROMLESS N-CHANNEL MICROCONTROLLERS |
| COP404CN | COP404C ROMless CMOS Microcontrollers |
| COP410C | Single-Chip CMOS Microcontrollers |
| COP411C | Single-Chip CMOS Microcontrollers |
| COP310C | Single-Chip CMOS Microcontrollers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| COP404CN | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:COP404C ROMless CMOS Microcontrollers |
| COP404LSN-5 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:COP404LSN-5 ROMLESS N-CHANNEL MICROCONTROLLERS |
| COP404N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-Bit Microcontroller |
| COP410C | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Single-Chip CMOS Microcontrollers |
| COP410C-XXX/D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-Bit Microcontroller |
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