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參數(shù)資料
| 型號： | CDB4382A |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | 114 dB, 192 kHz 8-channel D/A Converter |
| 中文描述： | 114分貝192千赫8通道D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 33/47頁 |
| 文件大?。?/td> | 685K |
| 代理商： | CDB4382A |
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DS618PP1
33
CS4382A
5.1.5
Power Down (PDN)
Default = 1
0 - Disabled
1 - Enabled
Function:
The entire device will enter a low-power state when this function is enabled, and the contents of the control
registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be dis-
abled before normal operation in Control Port mode can occur.
5.2
Mode Control 2 (address 02h)
5.2.1
Digital Interface Format (dif)
Default = 000 - Format 0 (Left Justified, up to 24-bit data)
Function:
These bits select the interface format for the serial audio input. The Functional Mode bits determine wheth-
er PCM or DSD mode is selected.
PCM Mode:
The required relationship between the Left/Right clock, serial clock and serial data is defined
by the Digital Interface Format and the options are detailed in Figures 7-12.
DIF1
DIF0
DESCRIPTION
0
0
Left Justified, up to 24-bit data
0
1
I
2
S, up to 24-bit data
1
0
Right Justified, 16-bit data
1
1
Right Justified, 24-bit data
0
0
Right Justified, 20-bit data
0
1
Right Justified, 18-bit data
1
0
Reserved
1
1
Reserved
DSD Mode:
The relationship between the oversampling ratio of the DSD audio data and the required Mas-
ter clock to DSD data rate is defined by the Digital Interface Format pins.
DIF2
DIF1
DIFO
0
0
0
64x oversampled DSD data with a 4x MCLK to DSD data rate
0
0
1
64x oversampled DSD data with a 6x MCLK to DSD data rate
0
1
0
64x oversampled DSD data with a 8x MCLK to DSD data rate
0
1
1
64x oversampled DSD data with a 12x MCLK to DSD data rate
1
0
0
128x oversampled DSD data with a 2x MCLK to DSD data rate
1
0
1
128x oversampled DSD data with a 3x MCLK to DSD data rate
1
1
0
128x oversampled DSD data with a 4x MCLK to DSD data rate
1
1
1
128x oversampled DSD data with a 6x MCLK to DSD data rate
7
6
5
4
3
2
1
0
Reserved
0
DIF2
0
DIF1
0
DIF0
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
DIF2
0
0
0
0
1
1
1
1
Format
0
1
2
3
4
5
-
-
FIGURE
7
8
9
10
11
12
Table 5. Digital Interface Formats - PCM Mode
DESCRIPTION
Table 6. Digital Interface Formats - DSD Mode
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CDB4382 | 114 dB, 192 kHz 8-Channel D/A Converter |
| CDB4383 | RES 1K-OHM 1% 0.10W 50PPM MET-FILM AXIAL BULK MIL-R-10509 |
| CDB4384 | 103 dB, 192 kHz 8-Channel D/A Converter |
| CDB4385 | 114 dB, 192kHz 8-CHANNEL D/A CONVERTER |
| CDB4390 | RESISTOR-1K, 1/10W, 1% MFILM, RN55C |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDB4383 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:114 dB, 192 kHz 8-Channel D/A Converter |
| CDB4384 | 功能描述:音頻 IC 開發(fā)工具 Eval Bd 8-Ch DAC w/DSD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
| CDB4385 | 功能描述:音頻 IC 開發(fā)工具 Eval Bd 8-Ch DAC w/DSD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
| CDB4390 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:24-Bit, Stereo D/A Converter for Digital Audio |
| CDB4391 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:24-Bit, 192 kHz Stereo DAC with Volume Control |
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