1. PIN DESCRIPTION........................." />
參數(shù)資料
型號： CDB4382A
廠商： Cirrus Logic, Inc.
英文描述： 114 dB, 192 kHz 8-channel D/A Converter
中文描述： 114分貝192千赫8通道D / A轉(zhuǎn)換
文件頁數(shù)： 2/47頁
文件大?。?/td> 685K
代理商： CDB4382A
2
DS618PP1
CS4382A
TABLE OF CONTENTS
2. CHARACTERISTICS AND SPECIFICATIONS.......................................................................... 8
3. APPLICATIONS ....................................................................................................................... 20
3.1 Master Clock..................................................................................................................... 20
3.2 Mode Select...................................................................................................................... 20
3.3 Digital Interface Formats .................................................................................................. 22
3.4 Oversampling Modes........................................................................................................ 23
3.5 Interpolation Filter............................................................................................................. 23
3.6 De-Emphasis.................................................................................................................... 23
3.7 ATAPI Specification.......................................................................................................... 24
3.8 Direct Stream Digital (DSD) Mode.................................................................................... 25
3.9 Grounding and Power Supply Arrangements................................................................... 25
3.9.1 Capacitor Placement............................................................................................ 25
3.10 Analog Output and Filtering............................................................................................ 25
3.11 Mute Control................................................................................................................... 26
3.12 Recommended Power-Up Sequence............................................................................. 27
3.12.1 Hardware Mode ................................................................................................. 27
3.12.2 Software Mode................................................................................................... 27
3.13 Recommended Procedure for Switching Operational Modes......................................... 27
3.14 Control Port Interface ..................................................................................................... 28
3.14.1 MAP Auto Increment.......................................................................................... 28
3.14.2 I
2
C Mode............................................................................................................ 28
3.14.2.1 I
2
C Write ............................................................................................ 28
3.14.2.2 I
2
C Read............................................................................................ 29
3.14.3 SPI Mode........................................................................................................ 30
3.14.3.1 SPI Write............................................................................................ 30
3.15 Memory Address Pointer (MAP) ............................................................................... 30
4. REGISTER QUICK REFERENCE............................................................................................ 31
5. REGISTER DESCRIPTION...................................................................................................... 32
5.1 Mode Control 1 (address 01h).......................................................................................... 32
5.1.1 Control Port Enable (CPEN)................................................................................ 32
5.1.2 Freeze Controls (Freeze)..................................................................................... 32
5.1.3 Master Clock DIVIDE ENABLE (mclkdiv) ............................................................ 32
5.1.4 DAC Pair Disable (DACx_DIS)............................................................................ 32
5.1.5 Power Down (PDN).............................................................................................. 33
5.2 Mode Control 2 (address 02h)......................................................................................... 33
5.2.1 Digital Interface Format (dif) ................................................................................ 33
5.2.2 Mode Control 3 (address 03h)............................................................................ 34
5.2.3 Soft Ramp AND Zero Cross CONTROL (SZC) ................................................... 34
5.2.4 Single Volume Control (Snglvol).......................................................................... 34
5.2.5 Soft Volume Ramp-Up after Error (RMP_UP) ..................................................... 35
5.2.6 MUTEC Polarity (MUTEC+/-)............................................................................... 35
5.2.7 Auto-Mute (AMUTE) ........................................................................................... 35
5.3 Mutec Pin Control (MUTEC)............................................................................................. 35
5.4 Filter Control (address 04h)............................................................................................. 36
5.4.1 Interpolation Filter Select (FILT_SEL).................................................................. 36
5.4.2 De-Emphasis Control (DEM) ............................................................................... 36
5.4.3 Soft Ramp-Down before Filter Mode Change (RMP_DN)................................... 36
5.5 Invert Control (address 05h)............................................................................................ 37
5.5.1 Invert Signal Polarity (Inv_Xx).............................................................................. 37
5.6 Mixing Control Pair 1 (Channels A1 & B1)(address 06h)
Mixing Control Pair 2 (Channels A2 & B2)(address 09h)
相關(guān)PDF資料
PDF描述
CDB4382 114 dB, 192 kHz 8-Channel D/A Converter
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CDB4383 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:114 dB, 192 kHz 8-Channel D/A Converter
CDB4384 功能描述:音頻 IC 開發(fā)工具 Eval Bd 8-Ch DAC w/DSD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V
CDB4385 功能描述:音頻 IC 開發(fā)工具 Eval Bd 8-Ch DAC w/DSD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V
CDB4390 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:24-Bit, Stereo D/A Converter for Digital Audio
CDB4391 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:24-Bit, 192 kHz Stereo DAC with Volume Control
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