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參數(shù)資料
| 型號： | CDB4382A |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | 114 dB, 192 kHz 8-channel D/A Converter |
| 中文描述： | 114分貝192千赫8通道D / A轉換 |
| 文件頁數(shù)： | 20/47頁 |
| 文件大小： | 685K |
| 代理商： | CDB4382A |
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20
DS618PP1
CS4382A
3. APPLICATIONS
The CS4382A serially accepts twos complement formatted PCM data at standard audio sample rates including 48,
44.1 and 32 kHz in SSM, 96, 88.2 and 64 kHz in DSM, and 192, 176.4 and 128 kHz in QSM. Audio data is input via
the serial data input pins (SDINx). The Left/Right Clock (LRCK) determines which channel is currently being input
on SDINx, and the Serial Clock (SCLK) clocks audio data into the input data buffer.
The CS4382A can be configured in hardware mode by the M0, M1, M2 , M3 and DSD_EN pins and in software
mode through I
2
C or SPI.
3.1
Master Clock
MCLK/LRCK must be an integer ratio as shown in Table 1. The LRCK frequency is equal to Fs, the frequen-
cy at which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio is detected
automatically during the initialization sequence by counting the number of MCLK transitions during a single
LRCK period. Internal dividers are then set to generate the proper internal clocks. Table 1 illustrates several
standard audio sample rates and the required MCLK and LRCK frequencies. Please note there is no re-
quired phase relationship, but MCLK, LRCK and SCLK must be synchronous.
3.2
Mode Select
In hardware mode operation is determined by the Mode Select pins. The state of these pins are continually
scanned for any changes. These pins require connection to supply or ground as outlined in figure 6. For
M0, M1, M2 supply is VLC and for M3 and DSD_EN supply is VLS. Tables 2 - 4 show the decode of these
pins.
In software mode the operational mode and data format are set in the FM and DIF registers. “Parameter
Definitions” on page 41.
Speed Mode
(sample-rate range)
Sample
Rate
(kHz)
MCLK (MHz)
Software
mode only
MCLK Ratio
256x
8.1920
11.2896
12.2880
128x
8.1920
11.2896
12.2880
64x
11.2896
12.2880
384x
12.2880
16.9344
18.4320
192x
12.2880
16.9344
18.4320
96x
16.9344
18.4320
512x
16.3840
22.5792
24.5760
256x
16.3840
22.5792
24.5760
128x
22.5792
24.5760
768x
24.5760
33.8688
36.8640
384x
24.5760
33.8688
36.8640
192x
33.8688
36.8640
1024x*
32.7680
45.1584
49.1520
512x*
32.7680
45.1584
49.1520
256x*
45.1584
49.1520
Single-Speed
(4 to 50 kHz)
32
44.1
48
MCLK Ratio
Double-Speed
(50 to 100 kHz)
64
88.2
96
MCLK Ratio
Quad-Speed
(100 to 200 kHz)
Note:
These modes are only available in software mode by setting the MCLKDIV bit = 1.
176.4
192
Table 1. Common Clock Frequencies
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| CDB4382 | 114 dB, 192 kHz 8-Channel D/A Converter |
| CDB4383 | RES 1K-OHM 1% 0.10W 50PPM MET-FILM AXIAL BULK MIL-R-10509 |
| CDB4384 | 103 dB, 192 kHz 8-Channel D/A Converter |
| CDB4385 | 114 dB, 192kHz 8-CHANNEL D/A CONVERTER |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CDB4383 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:114 dB, 192 kHz 8-Channel D/A Converter |
| CDB4384 | 功能描述:音頻 IC 開發(fā)工具 Eval Bd 8-Ch DAC w/DSD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
| CDB4385 | 功能描述:音頻 IC 開發(fā)工具 Eval Bd 8-Ch DAC w/DSD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
| CDB4390 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:24-Bit, Stereo D/A Converter for Digital Audio |
| CDB4391 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:24-Bit, 192 kHz Stereo DAC with Volume Control |
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