參數(shù)資料
型號: C3ENPB0-DS
英文描述: 4 Mbit (512 Kbit x 8) ZEROPOWER® SRAM
中文描述: ? - 3E的網(wǎng)絡(luò)處理器的數(shù)據(jù)資料硅修訂買0
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代理商: C3ENPB0-DS
94
CHAPTER 3: ELECTRICAL SPECIFICATIONS
C3ENPA1-DS/D REV 03
MOTOROLA GENERAL BUSINESS INFORMATION
BMU Timing
Specifications
The BMU timing specifications are shown in
Figure24
and described in
Table 49
.
The BMU synchronous DRAM interface is PC100-compliant and designed to work with
industry standard SDRAM components with 12 or fewer address lines. The information
below is intended to provide the output, setup, and hold data required to design this
interface without duplicating the transaction waveform diagrams in SDRAM data sheets.
Figure 24
BMU Timing Diagram
MDCLK
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
M_ctl
MAn
MDn
(output)
MDn
(input)
T
mc
T
mdo
T
mco
T
mao
T
mdv
T
mds
T
mdz
T
mdh
Table 49
BMU Timing Description
SYMBOL
Tmc
Tmco
Tmao
Tmds
Tmdh
Tmdo
Tmdz
Tmdv
PARAMETER
BMU Cycle Time
BMU Ctrl Output
BMU Addr Output
BMU Data Setup
BMU Data Hold
BMU Data Output
BMU Data Clk to Tri*
BMU Data Clk to Driven*
MIN
8.0
0.8
0.8
0.5
1.1
0.8
0.8
0.8
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
3.9
3.9
4.5
4.5
4.5
*
Not fully tested, values based on design/characterization.
F
n
.
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