參數(shù)資料
型號： C3ENPB0-DS
英文描述： 4 Mbit (512 Kbit x 8) ZEROPOWER® SRAM
中文描述： ? - 3E的網(wǎng)絡(luò)處理器的數(shù)據(jù)資料硅修訂買0
文件頁數(shù)： 49/114頁
文件大?。?/td> 1893K
代理商： C3ENPB0-DS
Pin Descriptions Grouped by Function
49
MOTOROLA GENERAL BUSINESS INFORMATION
C3ENPA1-DS/D REV 03
Fabric Processor Interface
Signals
The FP has logical signal interfaces: a receive data interface and a transmit data interface,
each with its own control, data, and clock signals. The interface has the following
characteristic:
The interface clocks FRXCLK and FTXCLK can have a different frequency from the core
C-3e NP clock frequency. The FP supports a fabric interface frequency from 10MHz to
125MHz.
FRXCLK and FTXCLK can be independent of each other; typically they have the same
frequency, but are allowed to be skewed relative to each other.
Each data bus can be configured for widths of 8 (data bits 7:0 are used), or 16 (bits 15:0). In
8bit mode, data bits 15:8 are unused.
The following tables list the Fabric Interface pin mappings:
Utopia1, Utopia2, Utopia3 ATM Mode mappings
are listed in
Table20
Utopia1, Utopia2, Utopia3 PHY Mode mappings
are listed in
Table 21
Table 19
Fabric Interface Signals
SIGNAL NAME
PIN #
TOTAL
TYPE
I/O
SIGNAL DESCRIPTION
FIN0 - FIN15
AD13, AC13, AB13, AG12, AF12, AE12, AD12,
AC12, AB12, AG11, AF11, AE11, AD11, AC11,
AB11, AG10
16
LVTTL
I
PD
Fabric Data Bus In
FOUT0 - FOUT15
AG17, AF17, AG16, AF16, AE16, AD16, AC16,
AB16, AG15, AF15, AE15, AD15, AC15, AB15,
AG14, AE14
16
LVTTL
O
Fabric Data Bus Out
FRXCLK
AG9
1
LVTTL
I
PD
I
PD
I
PD
, O Receive Control Signals
Receive Clock
FTXCLK
AE13
1
LVTTL
Transmit Clock
FRXCTL0 - FRXCTL2 &
FRXCTL6
AE10, AD10, AC10, AB10
4
LVTTL
FTXCTL0 - FRXCTL2 &
FTXCTL6
AC14, AB14, AG13, AF13
4
LVTTL
I
PD
, O Transmit Control Signals
TOTAL PINS
42
F
n
.
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