參數(shù)資料
型號: C3ENPB0-DS
英文描述: 4 Mbit (512 Kbit x 8) ZEROPOWER® SRAM
中文描述: ? - 3E的網(wǎng)絡(luò)處理器的數(shù)據(jù)資料硅修訂買0
文件頁數(shù): 35/114頁
文件大小: 1893K
代理商: C3ENPB0-DS
Pin Descriptions Grouped by Function
35
MOTOROLA GENERAL BUSINESS INFORMATION
C3ENPA1-DS/D REV 03
10/100 Ethernet (RMII) Configuration
Table 9
describes the 10/100BASE-T Ethernet Reduced Media Independent Interface
(RMII) signals. For each CP (0-15), you can implement one 10/100 Ethernet interface.
Table 9
10/100 Ethernet Signals
SIGNAL NAME*
CP
n
_0
CP
n
_1
PIN #
Table 7
Table 7
TOTAL
1
1
TYPE
LVTTL
LVTTL
I/O
O
PD
I
PU
LABEL
REF_CLK
CRS_DV
SIGNAL DESCRIPTION
Transmit and Receive Clock (50MHz)
Carrier Sense (CRS)/ Receive Data Valid (RX_DV). CRS indicates that
traffic is on the link, and is asserted if the signal is a 1 or an
alternating 1010... RX_DV indicates that a receive frame is in
progress and the data present on the RXD pins is valid. It is
asserted if this signal is a 1 for more than one cycle.
Transmit Data 0 (first on wire)
Transmit Data 1 (second on wire)
Receive Data 0 (first on wire)
Receive Data 1 (second on wire)
Transmit Enable. When asserted, the data on TXD is encoded and
transmitted on the twisted pair cable.
CP
n
_2
CP
n
_3
CP
n
_4
CP
n
_5
CP
n
_6
Table 7
Table 7
Table 7
Table 7
Table 7
1
1
1
1
1
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
O
PD
O
PU
I
PD
I
PU
O
PU
TXD(0)
TXD(1)
RXD(0)
RXD(1)
TX_EN
TOTAL PINS
7
*
n
can be from 0 to 7. See
Table7
.
F
n
.
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