參數(shù)資料
型號: C3ENPB0-DS
英文描述: 4 Mbit (512 Kbit x 8) ZEROPOWER® SRAM
中文描述: ? - 3E的網(wǎng)絡處理器的數(shù)據(jù)資料硅修訂買0
文件頁數(shù): 50/114頁
文件大?。?/td> 1893K
代理商: C3ENPB0-DS
50
CHAPTER 2: SIGNAL DESCRIPTIONS
C3ENPA1-DS/D REV 03
MOTOROLA GENERAL BUSINESS INFORMATION
When configuring two C-3e network processors back-to-back using the Fabric Port, set
up the transmit side of each C-3e network processor in Utopia ATM mode and the receive
side of each C-3e network processor in Utopia PHY mode.
Table 20
Utopia1*, 2*, 3 ATM Mode, C-3e Network Processor to Fabric Interface Pin Mapping
RECEIVE SIGNALS
TRANSMIT SIGNALS
C-3E NETWORK
PROCESSOR
I/O
UTOPIA
NOTE
C-3E NETWORK
PROCESSOR
I/O
UTOPIA
NOTE
FRXCTL0
Output
RxEnb*
Pullup or No
Connection
FTXCTL0
Output
TxEnb*
Pullup or No
Connection
FRXCTL1
Input
RxClav
FTXCTL1
Input
TxClav
FRXCTL2
Input
RxSOC
FTXCTL2
Output
TxSOC
FRXCTL6
Input
RxPrty
FTXCTL6
Output
TxPrty
*
Cell size must be 4Byte aligned. Both RxEnb and TxEnb are Active Low.
Table 21
Utopia1*, 2*, 3 PHY Mode, C-3e Network Processor to Fabric Interface Pin Mapping
RECEIVE SIGNALS
TRANSMIT SIGNALS
C-3E NETWORK
PROCESSOR
I/O
UTOPIA
NOTE
C-3E NETWORK
PROCESSOR
I/O
UTOPIA
NOTE
FRXCTL0
Input
TxEnb*
Pullup
FTXCTL0
Input
RxEnb*
Pullup
FRXCTL1
Output
TxClav
No Connection
FTXCTL1
Output
RxClav
No Connection
FRXCTL2
Input
TxSOC
FTXCTL2
Output
RxSOC
FRXCTL6
Input
TxPrty
FTXCTL6
Output
RxPrty
*
Cell size must be 4Byte aligned. Both TxEnb and RxEnb are Active Low.
F
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.
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