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參數(shù)資料
| 型號： | BXM80526B700128 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 700 MHz, MICROPROCESSOR, CPGA495 |
| 封裝： | MICRO, PGA2-495 |
| 文件頁數(shù)： | 60/74頁 |
| 文件大小： | 870K |
| 代理商： | BXM80526B700128 |
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Mobile Intel Celeron Processor (0.18) in BGA2 and Micro-PGA2 Packages
at 700MHz, 650 MHz, 600 MHz, 550 MHz, 500 MHz, 450 MHz,
Low-voltage 500 MHz, and Low-voltage 400A MHz
Datasheet
Order#-XXX
56
INIT# (I - 1.5V Tolerant)
The INIT# (Initialization) signal is asserted to reset integer registers inside the processor without
affecting the internal (L1 or L2) caches or the floating-point registers. The processor begins
execution at the power-on reset vector configured during power-on configuration. The processor
continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous input.
If INIT# is sampled active on RESET#'s active-to-inactive transition, then the processor executes
its built-in self test (BIST).
INTR (I - 1.5V Tolerant)
The INTR (Interrupt) signal indicates that an external interrupt has been generated. INTR becomes
the LINT0 signal when the APIC is enabled. The interrupt is maskable using the IF bit in the
EFLAGS register. If the IF bit is set, the processor vectors to the interrupt handler after
completing the current instruction execution. Upon recognizing the interrupt request, the processor
issues a single Interrupt Acknowledge (INTA) bus transaction. INTR must remain active until the
INTA bus transaction to guarantee its recognition.
LINT[1:0] (I - 1.5V Tolerant)
The LINT[1:0] (Local APIC Interrupt) signals must be connected to the appropriate pins/balls of
all APIC bus agents, including the processor and the system logic or I/O APIC component. When
APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and
LINT1 becomes NMI, a non-maskable interrupt. INTR and NMI are backward compatible with
the same signals for the Pentium processor. Both signals are asynchronous inputs.
Both of these signals must be software configured by programming the APIC register space to be
used either as NMI/INTR or LINT[1:0] in the BIOS. If the APIC is enabled at reset, then
LINT[1:0] is the default configuration.
LOCK# (I/O - GTL+)
The LOCK# (Lock) signal indicates to the system that a sequence of transactions must occur
atomically. This signal must be connected to the appropriate pins/balls on both agents on the
system bus. For a locked sequence of transactions, LOCK# is asserted from the beginning of the
first transaction through the end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for bus ownership, it waits until it observes
LOCK# deasserted. This enables the processor to retain bus ownership throughout the bus locked
operation and guarantee the atomicity of lock.
NMI (I - 1.5V Tolerant)
The NMI (Non-Maskable Interrupt) indicates that an external interrupt has been generated. NMI
becomes the LINT1 signal when the APIC is disabled. Asserting NMI causes an interrupt with an
internally supplied vector value of 2. An external interrupt-acknowledge transaction is not
generated. If NMI is asserted during the execution of an NMI service routine, it remains pending
and is recognized after the IRET is executed by the NMI service routine. At most, one assertion of
NMI is held pending. NMI is rising edge sensitive.
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