參數(shù)資料
型號: BXM80526B700128
廠商: INTEL CORP
元件分類: 微控制器/微處理器
英文描述: 64-BIT, 700 MHz, MICROPROCESSOR, CPGA495
封裝: MICRO, PGA2-495
文件頁數(shù): 22/74頁
文件大?。?/td> 870K
代理商: BXM80526B700128
Mobile Intel Celeron Processor (0.18) in BGA2 and Micro-PGA2 Packages
at 700MHz, 650 MHz, 600 MHz, 550 MHz, 500 MHz, 450 MHz,
Low-voltage 500 MHz, and Low-voltage 400A MHz
Datasheet
Order#-XXX
22
Table 20. Quick Start/Deep Sleep AC Specifications
1
TJ = 0°C to 100°C; VCC = 1.35V ±100 mV or 1.60V ±115 mV; VCCT = 1.50V ±115 mV
Symbol Parameter
Min Max Unit
Figure
Notes
T45
Stop Grant Cycle Completion to Clock Stop
100
BCLKs Figure 13
T46
Stop Grant Cycle Completion to Input Signals Stable
0
s
T47
Deep Sleep PLL Lock Latency
0
30
s
Note 2
T48
STPCLK# Hold Time from PLL Lock
0
ns
T49
Input Signal Hold Time from STPCLK# Deassertion
8
BCLKs Figure 13
NOTES:
1.
Input signals other than RESET# and BPRI# must be held constant in the Quick Start state.
2.
The BCLK Settling Time specification (T60) applies to Deep Sleep state exit under all conditions.
Table 21. Stop Grant/Sleep/Deep Sleep AC Specifications
TJ = C to 100°C; VCC = 1.35V ±100 mV or 1.60V ±115 mV; VCCT = 1.50V ±115 mV
Symbol
Parameter
Min Max Unit
Figure
T50
SLP# Signal Hold Time from Stop Grant Cycle Completion 100
BCLKs Figure 14
T51
SLP# Assertion to Input Signals Stable
0
ns
T52
SLP# Assertion to Clock Stop
10
BCLKs Figure 14
T54
SLP# Hold Time from PLL Lock
0
ns
T55
STPCLK# Hold Time from SLP# Deassertion
10
BCLKs Figure 14
T56
Input Signal Hold Time from SLP# Deassertion
10
BCLKs Figure 14
NOTE:
Input signals other than RESET# must be held constant in the Sleep state. The BCLK Settling Time specification
(T60) applies to Deep Sleep state exit under all conditions.
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