參數(shù)資料
型號(hào)： BXM80526B600256
廠商： INTEL CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： 64-BIT, 600 MHz, MICROPROCESSOR, CPGA495
封裝： MICRO PGA-495
文件頁(yè)數(shù)： 73/84頁(yè)
文件大?。?/td> 450K
代理商： BXM80526B600256
Mobile Pentium III Processor in BGA2 and Micro-PGA2 Packages Datasheet
Intel Corporation
67
RP# (I/O - GTL+)
The RP# (Request Parity) signal is driven by the request initiator and provides parity protection on
ADS# and REQ[4:0]#. RP# should be connected to the appropriate pins/balls on both agents on
the system bus.
A correct parity signal is high if an even number of covered signals are low and low if an odd
number of covered signals are low. This definition allows parity to be high when all covered
signals are high.
RS[2:0]# (I - GTL+)
The RS[2:0]# (Response Status) signals are driven by the response agent (the agent responsible for
completion of the current transaction) and must be connected to the appropriate pins/balls on both
agents on the system bus.
RSP# (I - GTL+)
The RSP# (Response Parity) signal is driven by the response agent (the agent responsible for
completion of the current transaction) during assertion of RS[2:0]#. RSP# provides parity
protection for RS[2:0]#. RSP# should be connected to the appropriate pins/balls on both agents on
the system bus.
A correct parity signal is high if an even number of covered signals are low, and it is low if an odd
number of covered signals are low. During Idle state of RS[2:0]# (RS[2:0]#=000), RSP# is also
high since it is not driven by any agent guaranteeing correct parity.
RSVD (TBD)
The RSVD (Reserved) signal is currently unimplemented but is reserved for future use. Leave this
signal unconnected. Intel recommends that a routing channel for this signal be allocated.
RTTIMPEDP (Analog)
The RTTIMPEDP (RTT Impedance/PMOS) signal is used to configure the on-die GTL+
termination. Connect the RTTIMPEDP signal to VSS with a 56.2-, 1% resistor.
SLP# (I - 1.5V Tolerant)
The SLP# (Sleep) signal, when asserted in the Stop Grant state, causes the processor to enter the
Sleep state. During the Sleep state, the processor stops providing internal clock signals to all units,
leaving only the Phase-Locked Loop (PLL) still running. The processor will not recognize snoop
and interrupts in the Sleep state. The processor will only recognize changes in the SLP#,
STPCLK# and RESET# signals while in the Sleep state. If SLP# is deasserted, the processor exits
Sleep state and returns to the Stop Grant state in which it restarts its internal clock to the bus and
APIC processor units.
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參數(shù)描述
BXM80536NC1400ES L7LS 制造商:Intel 功能描述:CELERON M,360,1.40GHZ,1M CACHE, 400MHZ FSB,1.26V,UFCPGA - Boxed Product (Development Kits)
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BXMP1003 制造商:SPECTRUM 制造商全稱(chēng):Spectrum Microwave, Inc. 功能描述:RF AMPLIFIER
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