參數(shù)資料
型號(hào): BXM80526B600256
廠商: INTEL CORP
元件分類: 微控制器/微處理器
英文描述: 64-BIT, 600 MHz, MICROPROCESSOR, CPGA495
封裝: MICRO PGA-495
文件頁(yè)數(shù): 20/84頁(yè)
文件大?。?/td> 450K
代理商: BXM80526B600256
Mobile Pentium III Processor in BGA2 and Micro-PGA2 Packages Datasheet
Intel Corporation
19
Table 10. Power Specifications for Fixed Frequency Mobile Pentium III Processor
TJ = 0°C to 100°C; VCC = 1.35V ±100 mV or 1.60V ±115 mV; V CCT = 1.50V ±115 mV
Symbol Parameter
Min
Typ
Max
Unit
Notes
VCC
Transient VCC for core logic
1.25
1.485
1.35
1.60
1.45
1.715
V
±100 mV
±115 mV, Note 7
VCC,DC
Static VCC for core logic
1.25
1.485
1.35
1.60
1.45
1.640
V
±100 mV
-115/+40 mV,
Note 2
VCCT
VCC for System Bus Buffers, Transient tolerance
1.385
1.50
1.615
V
±115 mV, Note 7
VCCT,DC
VCC for System Bus Buffers, Static tolerance
1.455
1.50
1.545
V
±3%, Note 2
ICC
Current for V CC at core frequency
at 400 MHz & 1.35V
at 500 MHz & 1.35V
at 450 MHz & 1.60V
at 500 MHz & 1.60V
7.8
9.5
9.6
10.6
A
Note 4
ICCT
Current for V CCT
2.5
A
Notes 3, 4
ICC,SG
Processor Stop Grant and
Auto Halt current
1.29
A
Notes 1,4
ICC,QS
Processor Quick Start and
Sleep current
994
mA
Notes 1,4
ICC,DSLP
Processor Deep Sleep
leakage current
700
mA
Notes 1,4
dICC/dt
VCC power supply current slew rate
1400
A/
s Notes 5, 6
dICCT/dt
VCCT power supply current slew rate
TBD
A/
s Notes 5, 6
NOTES:
1.
For ICC,SG , ICC,QS , and ICC,DSLP specifications in the case of 500MHz & 1.35V fixed frequency processor, refer to these
values listed in Table 9 at 1.35V.
2.
Static voltage regulation includes: DC output initial voltage set point adjust, output ripple and noise, output load ranges
specified in Table 10 above, temperature, and warm up.
3.
ICCT is the current supply for the system bus buffers, including the on-die termination.
4.
ICCx,max specifications are specified at VCC,DC max, VCCT,max, and 100°C and under maximum signal loading conditions.
5.
Based on simulations and averaged over the duration of any change in current. Use to compute the maximum inductance
and reaction time of the voltage regulator. This parameter is not tested.
6.
Maximum values specified by design/characterization at nominal VCC and VCCT.
7.
VCCx must be within this range under all operating conditions, including maximum current transients. VCCx must return to
within the static voltage specification, VCCx,DC, within 100
s after a transient event. The average of VCCx over time must
not exceed 1.65V, as an arbitrarily large time span may be used for this average.
The signals on the mobile Pentium III processor system bus are included in the GTL+ signal
group. These signals are specified to be terminated to VCCT . The DC specifications for these
signals are listed in Table 11 and the termination and reference voltage specifications for these
signals are listed in Table 12. The mobile Pentium III processor requires external termination and a
VREF. Refer to the Mobile Coppermine Processor GTL+ System Bus Layout Guideline for full
details of system VCCT and VREF requirements. The CMOS, Open-drain, and TAP signals are
designed to interface at 1.5V levels to allow connection to other devices. BCLK and PICCLK are
designed to receive a 2.5-V clock signal. The DC specifications for these signals are listed in
Table 13.
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