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| 型號(hào)： | BXM80526B600256 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 600 MHz, MICROPROCESSOR, CPGA495 |
| 封裝： | MICRO PGA-495 |
| 文件頁(yè)數(shù)： | 24/84頁(yè) |
| 文件大小： | 450K |
| 代理商： | BXM80526B600256 |
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Mobile Pentium III Processor in BGA2 and Micro-PGA2 Packages Datasheet
Intel Corporation
22
Table 14. System Bus Clock AC Specifications
1
TJ = 0°C to 100°C; VCC = 1.35V ±100 mV or 1.60V ±115 mV; V CCT = 1.50V ±115 mV
Symbol
Parameter
Min
Typ
Max
Unit
Figure
Notes
System Bus Frequency
100
MHz
T1
BCLK Period
10
ns
Figure 7
Note 2
T2
BCLK Period Stability
±250
ps
Notes 3, 4
T3
BCLK High Time
2.85
ns
Figure 7
at>1.7V
T4
BCLK Low Time
2.55
ns
Figure 7
at<0.7V
T5
BCLK Rise Time
0.175
0.875
ns
Figure 7
(0.9V – 1.6V)
T6
BCLK Fall Time
0.175
0.875
ns
Figure 7
(1.6V – 0.9V)
NOTES:
1.
All AC timings for GTL+ and CMOS signals are referenced to the BCLK rising edge at 1.25V. All CMOS signals are
referenced at 0.75V.
2.
The BCLK period allows a +0.5 ns tolerance for clock driver variation.
3.
Not 100% tested. Specified by design/characterization.
4.
Measured on the rising edge of adjacent BCLKs at 1.25V. The jitter present must be accounted for as a component of
BCLK skew between devices.
Table 15. Valid Mobile Pentium III Processor Frequencies
TJ = 0°C to 100°C; VCC = 1.35V ±100 mV or 1.60V ±115 mV; V CCT = 1.50V ±115 mV
BCLK Frequency
(MHz)
Frequency Multiplier
Core Frequency
(MHz)
Power-on Configuration
bits [25:22]
100
4.0
400
0010
100
4.5
450
0110
100
5
500
0000
100
6
600
1011
100
6.5
650
1111
NOTE:
While other combinations of bus and core frequencies are defined, operation at frequencies other than those listed
above will not be validated by Intel and are not guaranteed. The frequency multiplier is programmed into the
processor when it is manufactured and it cannot be changed.
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