參數(shù)資料
型號: BXM80526B600256
廠商: INTEL CORP
元件分類: 微控制器/微處理器
英文描述: 64-BIT, 600 MHz, MICROPROCESSOR, CPGA495
封裝: MICRO PGA-495
文件頁數(shù): 26/84頁
文件大?。?/td> 450K
代理商: BXM80526B600256
Mobile Pentium III Processor in BGA2 and Micro-PGA2 Packages Datasheet
Intel Corporation
24
Table 18. Reset Configuration AC Specifications
TJ = 0°C to 100°C; VCC = 1.35V ±100 mV or 1.60V ±115 mV; V CCT = 1.50V ±115 mV
Symbol Parameter
Min Max Unit
Figure
Notes
T16
Reset Configuration Signals (A[15:5]#, BREQ0#,
FLUSH#, INIT#, PICD0) Setup Time
4
BCLKs Figure 8.
Figure 9
Before
deassertion of
RESET#
T17
Reset Configuration Signals (A[15:5]#, BREQ0#,
FLUSH#, INIT#, PICD0) Hold Time
2
20
BCLKs Figure 8.
Figure 9
After clock that
deasserts
RESET#
T18
RESET#/PWRGOOD Setup Time
1
ms
Figure 11 Before
deassertion of
RESET#
1
NOTE:
At least 1 ms must pass after PWRGOOD rises above VIH25,minfrom Table 13 and BCLK meets its AC timing
specification until RESET# may be deasserted.
Table 19. APIC Bus Signal AC Specifications
1
TJ = 0°C to 100°C; VCC = 1.35V ±100 mV or 1.60V ±115 mV; V CCT = 1.50V ±115 mV
Symbol Parameter
Min
Max
Unit
Figure
Notes
T21
PICCLK Frequency
2
33.3
MHz
Note 2
T22
PICCLK Period
30
500
ns
Figure 6
T23
PICCLK High Time
10.5
ns
Figure 6
at>1.7V
T24
PICCLK Low Time
10.5
ns
Figure 6
at<0.7V
T25
PICCLK Rise Time
0.25
3.0
ns
Figure 6
(0.7V – 1.7V)
T26
PICCLK Fall Time
0.25
3.0
ns
Figure 6
(1.7V – 0.7V)
T27
PICD[1:0] Setup Time
8.0
ns
Figure 9
Note 3
T28
PICD[1:0] Hold Time
2.5
ns
Figure 9
Note 3
T29
PICD[1:0] Valid Delay
1.5
10.0
ns
Figure 8
Notes 3, 4, 5
NOTES:
1.
All AC timings for APIC signals are referenced to the PICCLK rising edge at 1.25V. All CMOS signals are referenced at
0.75V.
2.
The minimum frequency is 2 MHz when PICD0 is at 1.5V at reset. If PICD0 is strapped to VSS at reset then the minimum
frequency is 0 MHz.
3.
Referenced to PICCLK Rising Edge.
4.
For Open-drain signals, Valid Delay is synonymous with Float Delay.
5.
Valid delay timings for these signals are specified into 150
to 1.5V and 0 pF of external load. For real system timings
these specifications must be derated for external capacitance at 105 ps/pF.
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