參數(shù)資料
型號(hào)： BXM80526B600256
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 64-BIT, 600 MHz, MICROPROCESSOR, CPGA495
封裝： MICRO PGA-495
文件頁數(shù)： 45/84頁
文件大小： 450K
代理商： BXM80526B600256
Mobile Pentium III Processor in BGA2 and Micro-PGA2 Packages Datasheet
Intel Corporation
iii
Figures
Figure 1. Signal Groups of a Mobile Pentium III Processor/440BX or 440ZX-M
AGPset - Based System............................................................................... 2
Figure 2. Signal Groups of a Mobile Pentium III Processor/440MX Chipset - Based
System ....................................................................................................... 3
Figure 3. Clock Control States ..................................................................................... 8
Figure 4. Vcc Ramp Rate Requirement ...................................................................... 13
Figure 5. PLL RLC Filter............................................................................................ 15
Figure 6. PICCLK/TCK Clock Timing Waveform.......................................................... 27
Figure 7. BCLK Timing Waveform .............................................................................. 27
Figure 8. Valid Delay Timings .................................................................................... 28
Figure 9. Setup and Hold Timings .............................................................................. 28
Figure 10. Cold/Warm Reset and Configuration Timings.............................................. 29
Figure 11. Power-on Reset Timings ........................................................................... 29
Figure 12. Test Timings (Boundary Scan)................................................................... 30
Figure 13. Test Reset Timings ................................................................................... 30
Figure 14. Quick Start/Deep Sleep Timing.................................................................. 31
Figure 15. Stop Grant/Sleep/Deep Sleep Timing ......................................................... 32
Figure 16. Intel SpeedStep Technology/Deep Sleep Timing......................................... 33
Figure 17. BCLK/PICCLK Generic Clock Waveform .................................................... 35
Figure 18. Low to High, GTL+ Receiver Ringback Tolerance ....................................... 36
Figure 19. High to Low, GTL+ Receiver Ringback Tolerance ....................................... 37
Figure 20. Maximum Acceptable Overshoot/Undershoot Waveform ............................. 38
Figure 21. Surface-mount BGA2 Package - Top and Side View ................................... 41
Figure 22. Surface-mount BGA2 Package - Bottom View............................................. 42
Figure 23. Socketable Micro-PGA2 Package - Top and Side View ............................... 45
Figure 24. Socketable Micro-PGA2 Package - Bottom View......................................... 46
Figure 25. Pin/Ball Map - Top View ............................................................................ 47
Figure 26. PWRGOOD Relationship at Power On....................................................... 66
Figure 27. PLL Filter Specifications ............................................................................ 74
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