- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄295174 > BX805499030 (INTEL CORP) 64-BIT, 1600 MHz, MICROPROCESSOR, CPGA611 PDF資料下載
參數(shù)資料
| 型號： | BX805499030 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 1600 MHz, MICROPROCESSOR, CPGA611 |
| 封裝： | PGA-611 |
| 文件頁數(shù)： | 34/108頁 |
| 文件大?。?/td> | 2315K |
| 代理商： | BX805499030 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁當(dāng)前第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁
Dual-Core Intel Itanium Processor 9000 Series Datasheet
31
Electrical Specifications
The configuration pins (A[21:17]#) must be asserted the entire time RESET# is
asserted.
RESET# must be asserted before PWRGOOD is asserted.
The duration from the assertion of PWRGOOD to the deassertion of RESET# must
be 1 millisecond minimum.
After RESET# is deasserted, all the configuration, including pins A[21:17]#, must
remain valid for 2 BCLKs (minimum) to 3 BCLKs (maximum).
BCLK is shown as a time reference to the BCLK period. It is not a requirement that
this is BCLKn or BCLKp signal.
Configuration signals other than A[21:17]# must be asserted 4 BCLKs prior to the
deasserted edge of RESET# and must remain valid for 2 BCLKs (minimum) to 3
BCLKs (maximum) after the deasserted edge of RESET#.
Figure 2-5 outlines the timing relationship between the configuration pins, RESET# and
PWRGOOD for coldreset
Warm Reset Sequence:
PWRGOOD remains high throughout the entire sequence as power is already
available and stable to the processor.
The configuration pins (A[21:17]#) must be asserted the entire time RESET# is
asserted.
The duration from the assertion of RESET# to the deassertion of RESET# must be 1
millisecond minimum.
Figure 2-5. System Bus Reset and Configuration Timings for Cold Reset
000859b
BCLK
PWRGOOD
RESET#
Bus Ratio
(A[21:17]#)
TA = 1.15 ns minimum; (set up time to BCLK for deassertion edge of RESET#)
TB = 1 ms minimum for cold reset
TD = 2 BCLKs minimum, 3 BCLKs maximum
TE = 4 BCLKs minimum
TF = 2 BCLKs minimum, 3 BCLKs maximum
Additional
Configuration
Signals
TB
TD
TE
TF
TA
t
1
t
2
t
3
TC
TC = Bus ratio signals must be asserted no later than RESET#
t
-2
t
-1
t
0
t
-4
t
-3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BX805499040 | 64-BIT, 1600 MHz, MICROPROCESSOR, CPGA611 |
| BXA10-12D15-S | 2-OUTPUT DC-DC REG PWR SUPPLY MODULE |
| BXA200-48S12 | 1-OUTPUT 200 W DC-DC REG PWR SUPPLY MODULE |
| BXA40-48S15 | 1-OUTPUT 40 W DC-DC REG PWR SUPPLY MODULE |
| BXB100-48S15FLTJ | 1-OUTPUT 100 W DC-DC REG PWR SUPPLY MODULE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BX805499040 | 制造商:Intel 功能描述:DUAL-CORE ITANIUM 1.60 GHZ - Boxed Product (Development Kits) |
| BX805499050 | 制造商:Intel 功能描述:ITANIUM PROCESSOR 1.6 GHZ - Boxed Product (Development Kits) |
| BX80551KG2800HUS L8MA | 制造商:Intel 功能描述:BOXED INTEL XEON PROCESSOR 2.80 GHZ, 4M CACHE, 800 MHZ FSB, PASSIVE, FC-MPGA |
| BX80551PE2666FNS L8ZH | 制造商:Intel 功能描述:MPU PENTIUM D 90NM 2.66GHZ 775PIN FCLGA4 - Boxed Product (Development Kits) |
| BX80552352 S L96P | 制造商:Intel 功能描述:MPU Celeron 制造商:Intel 功能描述:MPU Celeron? D Processor 352 65nm 3.2GHz 775-Pin FCLGA4 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。