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參數資料
| 型號： | BX805499030 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 1600 MHz, MICROPROCESSOR, CPGA611 |
| 封裝： | PGA-611 |
| 文件頁數： | 16/108頁 |
| 文件大小： | 2315K |
| 代理商： | BX805499030 |
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Dual-Core Intel Itanium Processor 9000 Series Datasheet
15
Electrical Specifications
2
Electrical Specifications
This chapter describes the electrical specifications of the Dual-Core Intel Itanium 2
Processor 9000 series.
2.1
Dual-Core Intel Itanium 2 Processor 9000
Series System Bus
Most Dual-Core Intel Itanium 2 processor 9000 series signals use the Itanium
processor’s assisted gunning transceiver logic (AGTL+) signaling technology. The
termination voltage, VCTERM, is generated on the baseboard and is the system bus high
reference voltage. The buffers that drive most of the system bus signals on the
processor are actively driven to VCTERM during a low-to-high transition to improve rise
times and reduce noise. These signals should still be considered open-drain and require
termination to VCTERM which provides the high level. The processor system bus is
terminated to VCTERM at each end of the bus. There is also support of off-die
termination in which case the termination is provided by external resistors connected
to VCTERM.
AGTL+ inputs use differential receivers which require a reference signal (VREF). VREF is
used by the receivers to determine if a signal is a logical 0 or a logical 1. The processor
generates VREF on-die, thereby eliminating the need for an off-chip reference voltage
source.
2.1.1
System Bus Power Pins
VCTERM (1.2V) input pins on the processor provide power to the driver buffers and on-
die termination. The GND pins, in addition to the GND input at the power tab connector,
provide ground to the processor. Power for the processor core is provided through the
power tab connector by VCore, VCache, Vfixed. The 3.3V pin is included on the processor
to provide power to the system management bus (SMBus). The VCTERM, 3.3V, and GND
pins must remain electrically separated from each other.
2.1.2
System Bus No Connect
All pins designated as “N/C” or “No Connect” must remain unconnected.
2.2
System Bus Signals
2.2.1
Signal Groups
Table 2-1 contains processor system bus signals that have been combined into groups
by buffer type and whether they are inputs, outputs or bidirectional with respect to the
processor.
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