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參數(shù)資料
| 型號： | BX805499030 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 1600 MHz, MICROPROCESSOR, CPGA611 |
| 封裝： | PGA-611 |
| 文件頁數(shù)： | 107/108頁 |
| 文件大小： | 2315K |
| 代理商： | BX805499030 |
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98
Dual-Core Intel Itanium Processor 9000 Series Datasheet
Signals Reference
A.1.27
DPS# (I/O)
The Deferred Phase Enable (DPS#) signal is driven to the bus on the second clock of
the Request Phase on the Ab[3]# pin. DPS# is asserted if a requesting agent supports
transaction completion using the Deferred Phase. A requesting agent that supports the
Deferred Phase will always assert DPS#. A requesting agent that does not support the
Deferred Phase will always deassert DPS#.
A.1.28
DRDY# (I/O)
The Data Ready (DRDY#) signal is asserted by the data driver on each data transfer,
indicating valid data on the data bus. In a multi-cycle data transfer, DRDY# can be
deasserted to insert idle clocks.
DRDY# is replicated three times to enable partitioning of data paths in the system
agents. This copy of the Data Ready signal (DRDY#) is an input as well as an output.
A.1.29
DRDY_C1# (O)
DRDY# is a copy of the Data Ready signal. This copy of the Data Phase data-ready
signal (DRDY_C1#) is an output only.
A.1.30
DRDY_C2# (O)
DRDY# is a copy of the Data Ready signal. This copy of the Data Phase data-ready
signal (DRDY_C2#) is an output only.
A.1.31
DSZ[1:0]# (I/O)
The Data Size (DSZ[1:0]#) signals are transferred on REQb[4:3]# signals in the
second clock of the Request Phase by the requesting agent. The DSZ[1:0]# signals
define the data transfer capability of the requesting agent. For the processor, DSZ# =
01, always.
A.1.32
EXF[4:0]# (I/O)
The Extended Function (EXF[4:0]#) signals are transferred on the A[7:3]# pins by the
requesting agent during the second clock of the Request Phase. The signals specify any
special functional requirement associated with the transaction based on the requestor
mode or capability. The signals are defined in Table A-8.
Table A-8.
Extended Function Signals
Extended Function
Signal
Signal Name Alias
Function
EXF[4]#
Reserved
EXF[3]#
SPLCK#/FCL#
Split Lock / Flush Cache Line
EXF[2]#
OWN#/CCL#
Memory Update Not Needed / Cache Cleanse
EXF[1]#
DEN#
Defer Enable
EXF[0]#
DPS#
Deferred Phase Supported
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