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參數(shù)資料
| 型號(hào)： | BX805499030 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 1600 MHz, MICROPROCESSOR, CPGA611 |
| 封裝： | PGA-611 |
| 文件頁數(shù)： | 23/108頁 |
| 文件大?。?/td> | 2315K |
| 代理商： | BX805499030 |
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Dual-Core Intel Itanium Processor 9000 Series Datasheet
21
Electrical Specifications
Trise
BCLKp Rise Time
All
333
500
667
ps
20–80%
Tfall
BCLKp Fall Time
All
333
500
667
ps
20–80%
VPP
Minimum Input Swing
All
600
mV
6
Notes:
1. The system clock skew is ±100 ps.
2. Measured on cross point of rising edge of BCLKp and falling edge of BCLKn. Long term jitter is defined as peak-to-peak variation
measured by accumulating a large number of clock cycles and recording peak-to-peak jitter.
3. Cycle-to-cycle jitter is defined as peak-to-peak variation measured over 10000 cycles peak-to-peak jitter.
4. Measured on cross point of rising edge of BCLKp and falling edge of BCLKn.
5. The system clock skew is ±60 ps.
6. VPPmin is defined as the minimum input differential voltage which will cause no increase in the clock receiver timing.
Table 2-11. SMBus AC Specifications
Symbol
Parameter
Minimum
Maximum
Unit
Notes
fSMSC
SMSC Clock Frequency
100
kHz
TSMSC
SMSC Clock Period
10
s
thigh
SMSC Clock High Time
4.0
s
1
Notes:
1. Please refer to Figure 2-2 for the Standard Microsystems Corporation (SMSC)* clock waveform.
tlow
SMSC Clock Low Time
4.7
s
trise
SMSC Clock Rise Time
1.0
s
tfall
SMSC Clock Fall Time
0.3
s
tVALID
SMBus Output Valid Delay
1.0
s
tSU
SMBus Input Setup Time
250
ns
tHLD
SMBus Input Hold Time
0
ns
tFREE
Bus Free Time
4.7
s
2
2. Bus Free Time is the minimum time allowed between request cycles.
Figure 2-1. Generic Clock Waveform
000615
Table 2-10. System Bus Clock Differential HSTL AC Specifications (Sheet 2 of 2)
Symbol
Parameter
System
Bus
Clock
(MHz)
Minimum
Typ
Maximum
Unit
Figure
Notes
80%
Trise
Rise Time
Tfall
Fall Time
High Time
Thigh
Low Time
Tlow
=
20%
Tfall
Thigh
Tlow
Tperiod
Tjitter
BCLKN
BCLKP
Vpp
=
Tperiod
Period
Tjitter
Long Term Peak-to-Peak Jitter
Peak-to-Peak Swing
=
Vpp
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