參數(shù)資料
型號(hào): BT261KPJ
元件分類: TVS-瞬態(tài)抑制二極管
英文描述: Transient Voltage Suppressor Diodes
中文描述: 視頻信號(hào)發(fā)生器
文件頁數(shù): 39/56頁
文件大小: 387K
代理商: BT261KPJ
Brooktree
33
L261_H
I
NTERNAL
R
EGISTERS
HCOUNT Register
Bt261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
HCOUNT Register
This 12-bit register specifies the maximum number of pixel clocks to generate per horizontal line. In phase-locked
applications, HCOUNT is the critical register that is resolution dependent. It should be programmed with the number
of pixels per line required, minus 1. The other timing-dependent registers, including noise gate, ZERO, CLAMP, and
HSYNC, will now all be programmed in terms of clock events, based upon the number of clocks per line defined in
HCOUNT. For example, the HSYNC stop register is programmed to set output low at count zero, signifying the fall-
ing edge of HSYNC or the beginning of the line. The HSYNC start value is programmed to toggle high at 4.75
μ
s into
the horizontal line, signifying the beginning of the back porch, for RS170A. The HSYNC start value in terms of a
12.27 MHz clock (square pixels NTSC) would be 59 clocks, or ~4.7
μ
s (see Figure 8).
The HCOUNT low and high registers are cascaded to form a 12-bit HCOUNT register. D4–D7 of HCOUNT high
are ignored during MPU write cycles and return a logical zero during MPU read cycles. The 12-bit HCOUNT register
is not updated until the write cycle to the HCOUNT high register. Thus, the writing sequence should be [HCOUNT
low] [HCOUNT high]. Values from $0000 (1) to $0FFF (4096) may be specified. This register should be written first
during initialization to minimize indeterminate output activity.
HCOUNT High
HCOUNT Low
Data Bit
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Cascaded Value
H11
H19
H9
H8
H7
H6
H5
H4
H3
H2
H1
H0
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