參數(shù)資料
型號: BT261KPJ
元件分類: TVS-瞬態(tài)抑制二極管
英文描述: Transient Voltage Suppressor Diodes
中文描述: 視頻信號發(fā)生器
文件頁數(shù): 36/56頁
文件大?。?/td> 387K
代理商: BT261KPJ
Brooktree
30
L261_H
Bt261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
I
NTERNAL
R
EGISTERS
CLAMP Start and Stop Registers
ZERO Start and Stop Registers
These two 16-bit registers specify the number of pixel clock cycles after the falling edge of noise-gated CSYNC* at
which to assert or negate the ZERO output. The [start value] sets this output high at the specified number of CLOCK
cycles following the falling edge of noise-gated CSYNC*. The [stop value] sets this output low at the specified num-
ber of CLOCK cycles following the falling edge of noise-gated CSYNC*. If [start value] = [stop value], ZERO will
remain a constant logical one. Values from $0000 (1) to $0FFF (4096) may be specified. There is a 3-pixel-clock
pipeline delay in clearing the horizontal counter when the part is used in phase-lock loop mode. When the pixel clock
is generated by dividing down an external oscillator, this delay is in oscillator clocks. Thus, output of this signal with
respect to CSYNC* may be delayed.
D4–D7 of ZERO start high are ignored during MPU write cycles and return a logical zero during MPU read cycles.
The 16-bit ZERO start register is not updated until the write cycle to the ZERO start high register. Thus, the writing
sequence should be [zero start low] [zero start high].
D4–D7 of ZERO stop high are ignored during MPU write cycles and return a logical zero during MPU read cycles.
The 16-bit ZERO stop register is not updated until the write cycle to the ZERO stop high register. Thus, the writing
sequence should be [zero stop low] [zero stop high].
Since an active high signal is need for the Bt218, Bt252, and Bt254 during non-acquisition intervals, the ZERO
output can be programmed to be within the horizontal retrace interval. In addition, these devices produce a significant
impulse on their video input following the zero pulse, which can affect clamping stability. So, the pulse is best posi-
tioned within the active CLAMP pulse to divert this energy. Both CLAMP and ZERO pins may be driven with the
same timing.
ZERO Start/Stop High
ZERO Start/Stop Low
Data Bit
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Cascaded Value
H11
H19
H9
H8
H7
H6
H5
H4
H3
H2
H1
H0
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