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參數(shù)資料
| 型號： | BT261KPJ |
| 元件分類： | TVS-瞬態(tài)抑制二極管 |
| 英文描述： | Transient Voltage Suppressor Diodes |
| 中文描述： | 視頻信號發(fā)生器 |
| 文件頁數(shù)： | 11/56頁 |
| 文件大?。?/td> | 387K |
| 代理商： | BT261KPJ |
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Brooktree
5
C
IRCUIT
D
ESCRIPTION
Horizontal Counter
L261_H
Bt261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
Horizontal Counter
The rising edge of pixel clock (CLOCK) increments a 12-bit horizontal counter
used to generate horizontal video timing information. The value of the counter is
compared to various registers to determine when signals are to be asserted (set
high) and negated (set low). $000 corresponds to the falling edge of CSYNC*.
When the part is used with an external high-speed oscillator and divided down to
generate the pixel clock, there is no pipeline delay between CSYNC* and count
zero. However, when the part is used in phase locked loop mode with an external
VCO, there is a three-pixel-clock pipeline delay between CSYNC* and count zero.
Horizontal Sync Separation
The Bt261 separates horizontal sync information from CSYNC* by use of the hor-
izontal noise gate register, which derives gated composite sync by removing equal-
ization and serration pulses at half-line intervals.
Two 12-bit noise gate start and stop registers specify at what horizontal count
(with pixel clock resolution) to respectively ignore or accept falling sync transi-
tions on CSYNC*.
The sync noise gating is provided to filter incorrect horizontal sync information
from noisy video signals. The noise gating also serves a second purpose: to filter
serration and equalization pulses at half-line intervals from CSYNC* during the
vertical retrace interval. This enables steady synchronization of horizontal sync in-
formation during vertical retrace intervals.
HSYNC Input/Output
The HSYNC output may be programmed to be either active high or active low.
The start value sets the rising edge and the stop value sets the falling edge of
HSYNC relative to count zero of the horizontal counter. The beginning or falling
edge of HSYNC is typically programmed to be coincident with the beginning of
the noise-gated CSYNC*.
The HSYNC output may be three-stated via the command register.
HSYNC may also be configured as an input, enabling external circuitry to generate
HSYNC and drive the phase comparator.
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| BT-27 | 功能描述:TERM BLOCK HIGH CURRENT 27CIRC RoHS:是 類別:連接器，互連式 >> 接線座 - 隔板塊 系列:BT 標準包裝:10 系列:Beau™ 38780 端接塊類型:阻隔塊 電路數(shù):15 導(dǎo)線入口數(shù)目:30 間距:0.438"（11.12mm） 行數(shù):2 電流:15A 電壓:300V 線規(guī):14-22 AWG 頂部端子:螺釘 底部端子:焊片 阻擋層類型:雙壁（雙） 特點:法蘭 顏色:黑 包裝:散裝 安裝類型:通孔 工作溫度:- 材料 - 絕緣體:聚對苯二甲酸丁二酯（PBT），玻璃纖維增強型 材料可燃性額定值:UL94 V-0 其它名稱:038780-111538780-1115387801115 |
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