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參數(shù)資料
| 型號： | BT261KPJ |
| 元件分類： | TVS-瞬態(tài)抑制二極管 |
| 英文描述： | Transient Voltage Suppressor Diodes |
| 中文描述： | 視頻信號發(fā)生器 |
| 文件頁數(shù)： | 30/56頁 |
| 文件大小： | 387K |
| 代理商： | BT261KPJ |
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Brooktree
24
L261_H
Bt261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
I
NTERNAL
R
EGISTERS
Command Register_3
Command Register_3
This command register may be written to or read by the MPU at any time and is not initialized. CR30 corresponds to D0
and is the least significant bit.
VSYNC Sample Register
This 8-bit register specifies the number of pixel clock cycles after the falling edge of nongated CSYNC* at which to
sample the CSYNC* signal each scan line. By doing this, two samples per line will be taken during the vertical in-
terval when half-line pulses are present. The FIELD gate is programmed with the horizontal counter values (which
use only noise-gated CSYNC*); when sampling of the input sync occurs, VSYNC will toggle one half-line earlier at
the beginning of field two as opposed to the beginning of field one. This register may be written to or read by the MPU
at any time and is not initialized. Values from $00 (1) to $FF (256) may be specified. A value of 1/8 HCOUNT is rec-
ommended (~8
μ
s for the 15.75 KHz line-rate video). This is different from the 1/4 and 3/4 HCOUNT required for
FIELD-gate start and stop values, and greater than the 5
μ
s maximum width of sync pulses. For a conventional video
input with negative-going syncs, this produces a negative-going VSYNC* at the number of clock cycles specified af-
ter the falling CSYNC* edge. There is a 3-pixel-clock pipeline delay in clearing the horizontal counter when the part
is used in phase-lock loop mode. When the pixel clock is generated by dividing down an external oscillator, this delay
is in oscillator clocks. Thus, the output of this signal with respect to CSYNC* may be delayed (see Figure 8).
OSC Count Low and High Registers
These two 4-bit registers specify the number of rising and falling edges of an OSC input the pixel clock output
(CLOCK) is to be low and high. Values from $02 (2) to $OE (15) may be specified. These registers may be written
to or read by the MPU at any time and are not initialized. A value of $00 results in no pixel clock generation while
the OSC inputs are used. The counters clock on both the rising and falling edge of the selected OSC input. For exam-
ple, values of 4, 4 in OSC count low and high would result in a pixel clock with one fourth the frequency of the os-
cillator.
CR37, CR30
Phase lock line count
(0000 0000)
(0000 0001)
(1111 1111)
1 scan line
2 scan lines
256 scan lines
These bits specify the number of consecutive scan lines for
which lock must be maintained. If lock is not maintained for
the specified number of scan lines, the phase limiter is dis-
abled only if command bit CR22 is a logical one. SR05 is set
to zero if lock is maintained for the specified number of scan
lines.
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| BT-27 | 功能描述:TERM BLOCK HIGH CURRENT 27CIRC RoHS:是 類別:連接器，互連式 >> 接線座 - 隔板塊 系列:BT 標準包裝:10 系列:Beau™ 38780 端接塊類型:阻隔塊 電路數(shù):15 導線入口數(shù)目:30 間距:0.438"（11.12mm） 行數(shù):2 電流:15A 電壓:300V 線規(guī):14-22 AWG 頂部端子:螺釘 底部端子:焊片 阻擋層類型:雙壁（雙） 特點:法蘭 顏色:黑 包裝:散裝 安裝類型:通孔 工作溫度:- 材料 - 絕緣體:聚對苯二甲酸丁二酯（PBT），玻璃纖維增強型 材料可燃性額定值:UL94 V-0 其它名稱:038780-111538780-1115387801115 |
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