參數(shù)資料
型號(hào)： BT261KPJ
元件分類： TVS-瞬態(tài)抑制二極管
英文描述： Transient Voltage Suppressor Diodes
中文描述： 視頻信號(hào)發(fā)生器
文件頁(yè)數(shù)： 1/56頁(yè)
文件大?。?/td> 387K
代理商： BT261KPJ
Brooktree
Brooktree Division Rockwell Semiconductor Systems, Inc. 9868 Scranton Road San Diego, CA 92121-3707
619-452-7580 1-800-2-BT-APPS FAX: 619-452-1249 Internet: apps@brooktree.com L261_H
Distinguishing Features
Programmable 12-bit Video Timing
Bidirectional HSYNC and CLOCK
Pins
Horizontal Sync Noise Gating
External VCO Support
Standard MPU Interface
TTL Compatible
+ 5 V Monolithic CMOS
28-pin PLCC Package
Typical Power Dissipation:
300˙mW
Applications
Image Processing
Video Digitizing
Desktop Publishing
Graphic Art Systems
The Bt261 HSYNC Line Lock Controller is designed specifically for image cap-
ture applications.
Either composite video or TTL composite sync information is input via
VIDEO. An internal sync separator separates horizontal and vertical sync infor-
mation. Programmable horizontal and vertical video timing enables recovery of
both standard and nonstandard timing information.
An external VCO may be used in conjunction with the on-chip phase com-
parator for implementation of clocks locked to the horizontal frequency.
Alternately, a high-speed clock (OSC) may be divided down to generate the
pixel clock. The phase of the generated pixel clock is adjusted to align with the
noise-gated CSYNC. The higher the OSC clock rate, the lower the pixel clock
jitter (the maximum being one half the OSC clock period). The OSC inputs may
be configured to be either TTL or ECL compatible. Thus, four TTL clocks, two
TTL clocks and one differential ECL clock, or two differential ECL clocks may
be used. The ECL clock inputs are designed to be driven by 10KH ECL using a
single +5 V supply.
The CLAMP and ZERO outputs are programmed by the MPU to DC restore
the video signal and to zero the Image Digitizer or A/D converter at the appro-
priate time.
Functional Block Diagram
30 MHz Pixel Clock Monolithic
CMOS HSYNC Line Lock Controller
Bt261
PCOUT
SYNC
Noise Gate
Horizontal
Video
Timing
Control
OSC1
OSC1*
OSC2
OSC2*
M
U
X
Horizontal
Counter
Vertical
SYNC
Processor
SYNC
Detect
Phase
Comparator
XTAL OSC to
Pixel Clock
Generator
3-State
Buffer
HSYNC
VIDEO
CLOCK
ZERO
CLAMP
HSYNC
CAPTURE
VSYNC*
FIELD
CSYNC*
D0–D7 RD* WR* A0
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