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參數(shù)資料
| 型號： | BT261KPJ |
| 元件分類： | TVS-瞬態(tài)抑制二極管 |
| 英文描述： | Transient Voltage Suppressor Diodes |
| 中文描述： | 視頻信號發(fā)生器 |
| 文件頁數(shù)： | 28/56頁 |
| 文件大小： | 387K |
| 代理商： | BT261KPJ |
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Brooktree
22
L261_H
Bt261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
I
NTERNAL
R
EGISTERS
Command Register_1
Command Register_1
This command register may be written to or read by the MPU at any time and is not initialized. CR10 corresponds
to D0 and is the least significant bit.
CR17
Interlaced or noninterlaced select
(0)
(1)
noninterlaced operation
interlaced operation
This bit specifies whether an interlaced or noninterlaced video
signal is being digitized. The MPU must write a logical zero fol-
lowed by a logical one to this bit to reset the status bit (SR00)
to a logical one.
CR16
CLOCK output disable
(0)
(1)
drive CLOCK output
three-state CLOCK out-
put
This bit specifies whether the CLOCK pin is three-stated (logi-
cal one) or is actively driven (logical zero). A logical one
enables an external pixel clock to drive the internal counters.
CR15
CSYNC* output disable
(0)
(1)
drive CSYNC* output
three-state CSYNC* out-
put
This bit specifies whether the CSYNC* output is three-stated
(logical one) or is actively driven (logical zero).
CR14
VSYNC* output disable
(0)
(1)
drive VSYNC* output
three-state VSYNC* out-
put
This bit specifies whether the VSYNC* output is three-stated
(logical one) or is actively driven (logical zero).
CR13
HSYNC output disable
(0)
(1)
drive HSYNC output
three-state HSYNC out-
put
This bit specifies whether the HSYNC output is three-stated
(logical one) or is actively driven with the internally generated
HSYNC signal (logical zero). If external circuitry is driving the
HSYNC pin, this bit must be set to a logical one.
CR12
Reset lock loss status bit
(0)
(1)
set status bit SR00
inactive
This bit sets SR00, which is used to indicate loss of lock. The
MPU must write a logical zero to this bit to restart the process.
CR11
Phase comparator input select
(0)
(1)
HSYNC pin
internally generated
HSYNC
One input to the phase comparator is recovered composite
sync. The other input to the phase comparator is specified by
this bit to be either the internally generated HSYNC or the
HSYNC pin. When an external source is driving the HSYNC
pin, this bit should be set to a logical zero.
CR10
Phase limit enable
(0)
(1)
inhibit phase limiting
enable phase limiting
If this bit is a logical one, both horizontal sync signals (recov-
ered and either internally or externally generated) must be
present to adjust the VCO frequency. If one is missing, the
VCO frequency is not adjusted. If this bit is a logical zero, a
missing horizontal sync signal will adjust the VCO frequency.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BT26P | 制造商:Banner Engineering 功能描述:FIBER BT26P |
| BT26S | 制造商:Banner Engineering 功能描述:Sensor, Fiber Optic, Assembly, Bifurcated 制造商:Banner Engineering 功能描述:FIBER OPTIC SENSOR 制造商:Banner Engineering 功能描述:FIBER OPTIC SENSOR; Fiber Optic Sensor Type:Bifurcated Fibre; Type:Bifurcated Fibre ;RoHS Compliant: Yes |
| BT26SM900 | 制造商:Banner Engineering 功能描述:Sensor, Glass Fiber 制造商:Banner Engineering 功能描述:FIBER BT26SM900 ;ROHS COMPLIANT: YES |
| BT26SMSS | 制造商:Banner Engineering 功能描述:Sensor, Glass Fiber |
| BT-27 | 功能描述:TERM BLOCK HIGH CURRENT 27CIRC RoHS:是 類別:連接器，互連式 >> 接線座 - 隔板塊 系列:BT 標(biāo)準(zhǔn)包裝:10 系列:Beau™ 38780 端接塊類型:阻隔塊 電路數(shù):15 導(dǎo)線入口數(shù)目:30 間距:0.438"（11.12mm） 行數(shù):2 電流:15A 電壓:300V 線規(guī):14-22 AWG 頂部端子:螺釘 底部端子:焊片 阻擋層類型:雙壁（雙） 特點:法蘭 顏色:黑 包裝:散裝 安裝類型:通孔 工作溫度:- 材料 - 絕緣體:聚對苯二甲酸丁二酯（PBT），玻璃纖維增強型 材料可燃性額定值:UL94 V-0 其它名稱:038780-111538780-1115387801115 |
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