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參數(shù)資料
| 型號： | ASM5I961CG-32-ET |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | Low Voltage Zero Delay Buffer |
| 中文描述： | 961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | GREEN, TQFP-32 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 685K |
| 代理商： | ASM5I961CG-32-ET |
July 2005
rev 0.2
ASM5I961C
Low Voltage Zero Delay Buffer
9 of
15
Notice: The information in this document is subject to change without notice.
Where R
thja
is the thermal impedance of the package
(junction to ambient) and T
A
is the ambient temperature.
According to Table 9, the junction temperature can be
used to estimate the long-term device reliability. Further,
combining equation 1 and equation 2 results in a
maximum operating frequency for the ASM5I961C in a
series terminated transmission line system.
Table 10: Thermal package impedance of the 32
LQFP
Convection, LFPM
Still air
100 lfpm
200 lfpm
300 lfpm
400 lfpm
500 lfpm
Rthja (1P2S board), °C/W
80
70
61
57
56
55
T
J,MAX
should be selected according to the MTBF system
requirements and Table 9. R
thja
can be derived from Table
10. The R
thja
represent data based on 1S2P boards, using
2S2P boards will result in a lower thermal impedance
than indicated below. If the calculated maximum
frequency is below 200MHz, it becomes the upper clock
speed limit for the given application conditions. The
following two derating charts describe the safe frequency
operation range for the ASM5I961C. The charts were
calculated for a maximum tolerable die junction
temperature of 110°C, corresponding to an estimated
MTBF of 9.1 years, a supply voltage of 3.3V and series
terminated transmission line or capacitive loading.
Depending on a given set of these operating conditions
and the available device convection a decision on the
maximum operating frequency can be made. There are
no operating frequency limitations if a 2.5V power supply
or the system specifications allow for a MTBF of 4 years
(corresponding to a max. junction temperature of 120°C.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM5I961CG-32-LT | Low Voltage Zero Delay Buffer |
| ASM5I961C | Low Voltage Zero Delay Buffer |
| ASM5I961C-32-ET | Low Voltage Zero Delay Buffer |
| ASM5I961C-32-LT | Low Voltage Zero Delay Buffer |
| ASM5I961PG-32LR | Low Voltage Zero Delay Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I961CG-32-LT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I961P | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I961P-32LR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I961PG-32LR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I9653A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 1:8 LVCMOS PLL Clock Generator |
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