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參數(shù)資料
| 型號： | ASM5I961CG-32-ET |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | Low Voltage Zero Delay Buffer |
| 中文描述： | 961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | GREEN, TQFP-32 |
| 文件頁數(shù)： | 7/15頁 |
| 文件大?。?/td> | 685K |
| 代理商： | ASM5I961CG-32-ET |
July 2005
rev 0.2
a step in the waveform, this step is caused by the
impedance mismatch seen looking into the driver. The
parallel combination of the 36
series resistor plus the
output impedance does
combination of the line impedances. The voltage wave
launched down the two lines will equal:
VL = VS ( Zo / (Rs + Ro +Zo))
Zo = 50
|| 50
Rs = 36
|| 36
Ro = 14
VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57)
= 1.31V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.62V. It will then increment
towards the quiescent 3.0V in steps separated by one
round trip delay (in this case 4.0nS).
ASM5I961C
Low Voltage Zero Delay Buffer
7 of
15
Notice: The information in this document is subject to change without notice.
not match the parallel
Figure 5. Single versus Dual Waveforms
Since this step is well above the threshold region it will
not cause any false clock triggering, however designers
may be uncomfortable with unwanted reflections on the
line. To better match the impedances when driving
multiple lines the situation in Figure 6. should be used. In
this case the series terminating resistors are reduced
such that when the parallel combination is added to the
output buffer impedance the line impedance is perfectly
matched.
ASM5I961C
OUTPUT BUFFER
R
S
=22
14
+ 22
║
22
= 50
║
50
25
= 25
Figure 6. Optimized Dual Line Termination
Using the ASM5I961C in zero-delay applications
Nested clock trees are typical applications for the
ASM5I961C. Designs using the ASM5I961C as LVCMOS
PLL fanout buffer with zero insertion delay will show
significantly lower clock skew than clock distributions
developed from CMOS fanout buffers. The external
feedback option of the ASM5I961C clock driver allows for
its use as a zero delay buffer. By using the QFB output as
a feedback to the PLL the propagation delay through the
device is virtually eliminated. The PLL aligns the
feedback clock output edge with the clock input reference
edge resulting a near zero delay through the device. The
maximum insertion delay of the device in zero-delay
applications is measured between the reference clock
input and any output. This effective delay consists of the
static phase offset, I/O jitter (phase or long-term jitter),
feedback path delay and the output-to-output skew error
relative to the feedback output.
Calculation of part-to-part skew
The ASM5I961C zero delay buffer supports applications
where critical clock signal timing can be maintained
across several devices. If the reference clock inputs of
two or more ASM5I961C are connected together, the
maximum overall timing uncertainty from the common
CCLK input to any output is:
t
SK(PP)
= t
(
)
+ t
SK(O)
+ t
PD
, L
INE(FB)
+ t
JIT(
)
CF
This
maximum
timing
uncertainty
components: static phase offset, output skew, feedback
board trace delay and I/O (phase) jitter:
consist
of
4
Figure 7. ASM5I961C max. device-to-device skew
Due to the statistical nature of I/O jitter a rms value (1
σ
) is
specified. I/O jitter numbers for other confidence factors
(CF) can be derived from Table 8.
14
IN
Z
0
=50
R
S
=22
Z
0
=50
相關PDF資料 |
PDF描述 |
|---|---|
| ASM5I961CG-32-LT | Low Voltage Zero Delay Buffer |
| ASM5I961C | Low Voltage Zero Delay Buffer |
| ASM5I961C-32-ET | Low Voltage Zero Delay Buffer |
| ASM5I961C-32-LT | Low Voltage Zero Delay Buffer |
| ASM5I961PG-32LR | Low Voltage Zero Delay Buffer |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I961CG-32-LT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I961P | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I961P-32LR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I961PG-32LR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I9653A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 1:8 LVCMOS PLL Clock Generator |
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