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參數資料
| 型號： | ASM5I961CG-32-ET |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | Low Voltage Zero Delay Buffer |
| 中文描述： | 961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | GREEN, TQFP-32 |
| 文件頁數： | 3/15頁 |
| 文件大?。?/td> | 685K |
| 代理商： | ASM5I961CG-32-ET |
July 2005
rev 0.2
ASM5I961C
Low Voltage Zero Delay Buffer
3 of
15
Notice: The information in this document is subject to change without notice.
Table 2: FUNCTION TABLE
Control
Default
0
1
F_RANGE
0
PLL high frequency range. ASM5I961C input
reference and output clock frequency range is
100 – 200MHz
PLL low frequency range. ASM5I961C input
reference and output clock frequency range is
50 – 100MHz
OE
0
Outputs enabled
Outputs disabled (high–impedance state)
Table 3: ABSOLUTE MAXIMUM RATINGS
1
Symbol
Parameter
Min
Max
Unit
V
CC
V
IN
V
OUT
I
IN
I
OUT
T
S
Note: 1 These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature Range
–0.3
–0.3
–0.3
–40
3.6
V
V
V
mA
mA
°C
V
CC
+ 0.3
V
CC
+ 0.3
±20
±50
125
Table 4: DC CHARACTERISTICS
(V
CC
= 3.3V ± 5%, T
A
= -40°C to +85°C)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
V
IH
V
IL
V
OH
V
OL
Z
OUT
I
IN
C
IN
C
PD
I
CCA
I
CC
V
TT
Note: 1. The ASM5I961C is capable of driving 50
transmission lines on the incident edge. Each output drives one 50
parallel terminated transmission line to
a termination voltage of V
TT
. Alternatively, the device drives up two 50
series terminated transmission lines.
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Output Impedance
Input Current
Input Capacitance
Power Dissipation Capacitance
Maximum PLL Supply Current
Maximum Quiescent Supply Current
Output Termination Voltage
2.0
–0.3
2.4
VCC + 0.3
0.8
0.55
20
±120
10
5.0
TBD
V
V
V
V
μ
A
pF
pF
mA
mA
V
LVCMOS
LVCMOS
I
OH
= –20mA
1
I
OL
= 20mA
1
Per Output
V
CCA
Pin
All V
CC
Pins
14
4.0
8.0
2.0
V
CC
÷2
相關PDF資料 |
PDF描述 |
|---|---|
| ASM5I961CG-32-LT | Low Voltage Zero Delay Buffer |
| ASM5I961C | Low Voltage Zero Delay Buffer |
| ASM5I961C-32-ET | Low Voltage Zero Delay Buffer |
| ASM5I961C-32-LT | Low Voltage Zero Delay Buffer |
| ASM5I961PG-32LR | Low Voltage Zero Delay Buffer |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ASM5I961CG-32-LT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I961P | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I961P-32LR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I961PG-32LR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I9653A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 1:8 LVCMOS PLL Clock Generator |
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