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參數(shù)資料
| 型號(hào)： | ASM5I961CG-32-ET |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | Low Voltage Zero Delay Buffer |
| 中文描述： | 961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | GREEN, TQFP-32 |
| 文件頁(yè)數(shù)： | 5/15頁(yè) |
| 文件大?。?/td> | 685K |
| 代理商： | ASM5I961CG-32-ET |
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July 2005
rev 0.2
Table 6: DC CHARACTERISTICS
(V
CC
= 2.5V ± 5%, T
A
= –40° to 85°C)
ASM5I961C
Low Voltage Zero Delay Buffer
5 of
15
Notice: The information in this document is subject to change without notice.
Symbol
V
IH
V
IL
V
OH
V
OL
Z
OUT
I
IN
C
IN
C
PD
I
CCA
I
CC
V
TT
Note: 1.The ASM5I961C is capable of driving 50
transmission lines on the incident edge. Each output drives one 50
parallel terminated transmission line to
a termination voltage of V
TT
. Alternatively, the device drives up two 50
series terminated transmission lines.
Table 7: AC CHARACTERISTICS
(V
CC
= 2.5V ± 5%, T
A
= 40°C to +85°C)
1
Symbol
Characteristic
Characteristic
Min
1.7
–0.3
1.8
Typ
18
4.0
8.0
2.0
V
CC
÷2
Max
Unit
V
V
V
V
mA
pF
pF
mA
mA
V
Condition
LVCMOS
LVCMOS
I
OH
= –15mA
1
I
OL
= 15mA
1
Per Output
V
CCA
Pin
All V
CC
Pins
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Output Impedance
Input Current
Input Capacitance
Power Dissipation Capacitance
Maximum PLL Supply Current
Maximum Quiescent Supply Current
Output Termination Voltage
VCC + 0.3
0.7
0.6
26
±120
10
5.0
TBD
Min
Typ
Max
Unit
Condition
f
ref
Input Frequency
F_RANGE = 0
F_RANGE = 1
F_RANGE = 0
F_RANGE = 1
100
50
100
50
25
200
100
200
100
75
3.0
MHz
f
max
Maximum Output
Frequency
Reference Input Duty Cycle
TCLK Input Rise/Fall Time
Propagation Delay
(static phase offset)
Output–to–Output Skew
2
MHz
f
refDC
t
r
, t
f
%
nS
0.7 to 1.7V
t
(
)
CCLK to FB_IN
–80
120
pS
PLL locked
t
sk(O)
90
50
50
7.0
150
60
55
1.0
10
10
15
10
15
10
pS
DC
O
Output Duty Cycle
F_RANGE = 0
F_RANGE = 1
40
45
0.1
%
t
r
, t
f
t
PLZ,HZ
t
PZL,LZ
t
JIT(CC)
t
JIT(PER)
t
JIT(
)
t
lock
Note: 1 AC characteristics apply for parallel output termination of 50
to V
TT
.
2 See applications section for part–to–part skew calculation
3 See applications section for calculation for other confidence factors than 1
σ
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle–to–Cycle Jitter
Period Jitter
I/O Phase Jitter
Maximum PLL Lock Time
nS
nS
nS
pS
pS
nS
mS
0.6 to 1.8V
RMS (1
σ
)
3
RMS (1
σ
)
RMS (1
σ
)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM5I961CG-32-LT | Low Voltage Zero Delay Buffer |
| ASM5I961C | Low Voltage Zero Delay Buffer |
| ASM5I961C-32-ET | Low Voltage Zero Delay Buffer |
| ASM5I961C-32-LT | Low Voltage Zero Delay Buffer |
| ASM5I961PG-32LR | Low Voltage Zero Delay Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I961CG-32-LT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I961P | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I961P-32LR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I961PG-32LR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I9653A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 1:8 LVCMOS PLL Clock Generator |
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